Presentation 2017-11-07
Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST
Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A logic BIST scheme using multi-cycle test with partial observation has been proposed. In the scheme, the selection of flip-flops for partial observation plays an important role for improving the fault coverage and reducing the area overhead. This paper proposes a selection method of flip-flops for partial observation that can maximize the fault coverage under the limitation of the number of flip-flops. Experimental results show that the proposed method can obtain higher fault coverage than the existing flip-flop selection method and results in less area overhead.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) BIST / Scan Test / Multi-Cycle Test / Partial Observation
Paper # VLD2017-41,DC2017-47
Date of Issue 2017-10-30 (VLD, DC)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2017/11/6(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Kumamoto-Kenminkouryukan Parea
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2017 -New Field of VLSI Design-
Chair Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII)
Vice Chair Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT)
Secretary Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.)
Assistant / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST
Sub Title (in English)
Keyword(1) BIST
Keyword(2) Scan Test
Keyword(3) Multi-Cycle Test
Keyword(4) Partial Observation
1st Author's Name Shigeyuki Oshima
1st Author's Affiliation Kyushu Institute of Technology(Kyutech)
2nd Author's Name Takaaki Kato
2nd Author's Affiliation Kyushu Institute of Technology(Kyutech)
3rd Author's Name Senling Wang
3rd Author's Affiliation Ehime University(Ehime Univ.)
4th Author's Name Yasuo Sato
4th Author's Affiliation Kyushu Institute of Technology(Kyutech)
5th Author's Name Seiji Kajihara
5th Author's Affiliation Kyushu Institute of Technology(Kyutech)
Date 2017-11-07
Paper # VLD2017-41,DC2017-47
Volume (vol) vol.117
Number (no) VLD-273,DC-274
Page pp.pp.85-90(VLD), pp.85-90(DC),
#Pages 6
Date of Issue 2017-10-30 (VLD, DC)