Presentation 2017-11-07
Prospects of an Error-Correction Technique of Intra-Chip Data Transmission Using Time-Series Feature
Kentaro Kato, Masanori Natsui, Takahiro Hanyu,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper presents a top-down error-correction technique of intra-chip data transmission using time-series feature extracted by a recurrent neural network. By applying this method to data transfer between memory and processors in a microprocessor unit, we show that it is possible to improve the error correction performance without increasing the amount of transferred data due to redundancy.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Top-Down Error CorrectionRecurrent Neural NetworkTime-Series Feature
Paper # CPM2017-85,ICD2017-44,IE2017-70
Date of Issue 2017-10-30 (CPM, ICD, IE)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2017/11/6(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Kumamoto-Kenminkouryukan Parea
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2017 -New Field of VLSI Design-
Chair Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII)
Vice Chair Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT)
Secretary Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.)
Assistant / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Prospects of an Error-Correction Technique of Intra-Chip Data Transmission Using Time-Series Feature
Sub Title (in English)
Keyword(1) Top-Down Error CorrectionRecurrent Neural NetworkTime-Series Feature
1st Author's Name Kentaro Kato
1st Author's Affiliation Tohoku University(Tohoku Univ.)
2nd Author's Name Masanori Natsui
2nd Author's Affiliation Tohoku University(Tohoku Univ.)
3rd Author's Name Takahiro Hanyu
3rd Author's Affiliation Tohoku University(Tohoku Univ.)
Date 2017-11-07
Paper # CPM2017-85,ICD2017-44,IE2017-70
Volume (vol) vol.117
Number (no) CPM-275,ICD-276,IE-277
Page pp.pp.33-38(CPM), pp.33-38(ICD), pp.33-38(IE),
#Pages 6
Date of Issue 2017-10-30 (CPM, ICD, IE)