| Presentation | 2017-11-06 A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST Kyonosuke Watanabe, Satoshi Ohtake, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the miniaturization and high speed of large scale integrated circuits, it has become important to test delay faults. A transition fault that increase delay in a logic gate is one of the delay fault models. Since the detectable delay size of a fault depends on its test pattern, the test quality can not be evaluated sufficiently with fault coverage of the transition faults. As a method to evaluate delay test quality, statistical delay quality model (SDQM) has been proposed. Statistical delay quality level (SDQL) can be improved using tests generated by a commercially available timing aware ATPG tool. At present, methods of seed generation which convert test cubes for detecting faults into seeds are widely used. The care bit rate of the test cubes increases and the encodability ofsuch cubes becomes low when the methods are used with a timing aware ATPG. In this paper, we propose a method of SDQL-aware LFSR seed generation using a time expansion model of an LFSR. We also evaluate the effectiveness of the proposed method by experiments using ITC’99 benchmark circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BIST / LFSR / Seed Generation / Time Expansion Model / Transition Fault / SDQM |
| Paper # | VLD2017-35,DC2017-41 |
| Date of Issue | 2017-10-30 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2017/11/6(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto-Kenminkouryukan Parea |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.) |
| Assistant | / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST |
| Sub Title (in English) | |
| Keyword(1) | BIST |
| Keyword(2) | LFSR |
| Keyword(3) | Seed Generation |
| Keyword(4) | Time Expansion Model |
| Keyword(5) | Transition Fault |
| Keyword(6) | SDQM |
| 1st Author's Name | Kyonosuke Watanabe |
| 1st Author's Affiliation | Oita University(Oita Univ.) |
| 2nd Author's Name | Satoshi Ohtake |
| 2nd Author's Affiliation | Oita University(Oita Univ.) |
| Date | 2017-11-06 |
| Paper # | VLD2017-35,DC2017-41 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-273,DC-274 |
| Page | pp.pp.49-54(VLD), pp.49-54(DC), |
| #Pages | 6 |
| Date of Issue | 2017-10-30 (VLD, DC) |