| Presentation | 2017-11-06 Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control Yusuke Yoshida, Kimiyoshi Usami, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Embedded memory macros are major central building blocks of any microprocessor and greatly affect power dissipation. In this paper, we focus on the Standard Cell based Memory (SCM) as a digital memory instead of SRAM macros. We propose a dynamic multi body-bias control technique which keeps data retention margin comfortable and reduces leakage energy under the variations. Post layout simulation showed that the proposed approach allowed us to reduce leakage energy by 37% and 48% at the maximum as compared to the conventional body bias control and Multi-Vth designs, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Body Bias / Standard Cell based Memory / Low voltage operation / Low energy / Variation tolerance |
| Paper # | VLD2017-33,DC2017-39 |
| Date of Issue | 2017-10-30 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2017/11/6(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto-Kenminkouryukan Parea |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.) |
| Assistant | / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control |
| Sub Title (in English) | |
| Keyword(1) | Body Bias |
| Keyword(2) | Standard Cell based Memory |
| Keyword(3) | Low voltage operation |
| Keyword(4) | Low energy |
| Keyword(5) | Variation tolerance |
| 1st Author's Name | Yusuke Yoshida |
| 1st Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technology(SIT) |
| Date | 2017-11-06 |
| Paper # | VLD2017-33,DC2017-39 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-273,DC-274 |
| Page | pp.pp.37-42(VLD), pp.37-42(DC), |
| #Pages | 6 |
| Date of Issue | 2017-10-30 (VLD, DC) |