Presentation | 2017-11-06 Optimization of Cryptographic Hardware for Optimal Ate Pairing over BN Curves Tadayuki Ichihashi, Hiromitsu Awano, Makoto Ikeda, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | |
Paper # | VLD2017-30,DC2017-36 |
Date of Issue | 2017-10-30 (VLD, DC) |
Conference Information | |
Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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Conference Date | 2017/11/6(3days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Kumamoto-Kenminkouryukan Parea |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII) |
Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT) |
Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.) |
Assistant | / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Optimization of Cryptographic Hardware for Optimal Ate Pairing over BN Curves |
Sub Title (in English) | |
Keyword(1) | |
1st Author's Name | Tadayuki Ichihashi |
1st Author's Affiliation | The University of Tokyo(Tokyo Univ.) |
2nd Author's Name | Hiromitsu Awano |
2nd Author's Affiliation | The University of Tokyo(Tokyo Univ.) |
3rd Author's Name | Makoto Ikeda |
3rd Author's Affiliation | The University of Tokyo(Tokyo Univ.) |
Date | 2017-11-06 |
Paper # | VLD2017-30,DC2017-36 |
Volume (vol) | vol.117 |
Number (no) | VLD-273,DC-274 |
Page | pp.pp.19-24(VLD), pp.19-24(DC), |
#Pages | 6 |
Date of Issue | 2017-10-30 (VLD, DC) |