Presentation 2017-11-07
Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on β-Expansion by Eliminating Look-Up Table
Yuji Shindo, Kenshu Seto, Hao San,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We propose an area reduction method of digital circuit part in analog-to-digital converter (ADC) based on β-expansion. The digital parts of existing β-expansion based ADCs uses lookup tables (LUTs) to estimate effective β values and to convert non-binary numbers to binary numbers. Unfortunately, increasing the conversion precision of the ADCs increases the area of the LUTs. In this work, in order to eliminate the LUTs, we estimate the effective β values by Newton’s method and directly convert non-binary numbers to binary numbers. When the conversion precision of the ADCs is increased, the proposed method reduces the increase of the digital part area compared to the existing LUT-based method.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) AD Converter / High-Level Synthesis
Paper # VLD2017-44,DC2017-50
Date of Issue 2017-10-30 (VLD, DC)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2017/11/6(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Kumamoto-Kenminkouryukan Parea
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2017 -New Field of VLSI Design-
Chair Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII)
Vice Chair Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT)
Secretary Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.)
Assistant / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on β-Expansion by Eliminating Look-Up Table
Sub Title (in English)
Keyword(1) AD Converter
Keyword(2) High-Level Synthesis
1st Author's Name Yuji Shindo
1st Author's Affiliation Tokyo City University(TCU)
2nd Author's Name Kenshu Seto
2nd Author's Affiliation Tokyo City University(TCU)
3rd Author's Name Hao San
3rd Author's Affiliation Tokyo City University(TCU)
Date 2017-11-07
Paper # VLD2017-44,DC2017-50
Volume (vol) vol.117
Number (no) VLD-273,DC-274
Page pp.pp.101-104(VLD), pp.101-104(DC),
#Pages 4
Date of Issue 2017-10-30 (VLD, DC)