| Presentation | 2017-11-08 マルチコアプロセッサの効率的な設計検証に向けたプロセッサシミュレータの並列化 Kouki Kayamuro, Takahiro sasaki, Yuki Fukazawa, Toshio Kondo, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Generally, HDL simulation is used for development and verification of processor design. However, the simulation speed is not fast. The simulation speed is improved by fast-skip technique which runs a the benchmark program before Region of Interest (ROI) using a fast function simulator, and pass architecture state to HDL simulator and perform detailed simulation on HDL simulator. Nevertheless, fast-skip is not effective for multi-core processor design, because the conventional functional simulator is slow down depending on the number of target core. Although faster parallelized multi-core processor simulators have been proposed to improve simulation speed, most of these simulator change the simulation results every execution. Therefore conventional simulators are not suitable for processor verification phases, because the difference of results affects to the behavior of ROI. In this paper, we propose parallel simulation method with reproducibility of simulation results. According to the evaluation results, proposed method achieved both 7 times faster simulation speed at the maximum and reproducibility of results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multi-core processor / design verification / co-simulation / parallel simulation / multi-thread |
| Paper # | CPSY2017-45 |
| Date of Issue | 2017-10-31 (CPSY) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2017/11/6(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto-Kenminkouryukan Parea |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.) |
| Assistant | / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN-ONLY |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | |
| Sub Title (in English) | |
| Keyword(1) | multi-core processor |
| Keyword(2) | design verification |
| Keyword(3) | co-simulation |
| Keyword(4) | parallel simulation |
| Keyword(5) | multi-thread |
| 1st Author's Name | Kouki Kayamuro |
| 1st Author's Affiliation | Mie University(Mie Univ.) |
| 2nd Author's Name | Takahiro sasaki |
| 2nd Author's Affiliation | Mie University(Mie Univ.) |
| 3rd Author's Name | Yuki Fukazawa |
| 3rd Author's Affiliation | Mie University(Mie Univ.) |
| 4th Author's Name | Toshio Kondo |
| 4th Author's Affiliation | Mie University(Mie Univ.) |
| Date | 2017-11-08 |
| Paper # | CPSY2017-45 |
| Volume (vol) | vol.117 |
| Number (no) | CPSY-278 |
| Page | pp.pp.53-58(CPSY), |
| #Pages | 6 |
| Date of Issue | 2017-10-31 (CPSY) |