Presentation 2017-11-07
DCNN Training with Short Bit Length Format Considering Loss of Trailing Digits
Shin-ichi O'uchi, Hiroshi Fuketa, Ryousei Takano,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Loss of trailing digits in training deep convolutional neural network (DCNN) is considered to implement training with a format shorter than 16-bit floating format. As a result, we propose an 8-bit training method. The method improves inference accuracy compared to 16-bit floating format in training AlexNet. Simultaneously, the hardware size is reduced by half compared to the 16-bit hardware.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Deep convolutional neural network (DCNN) / AlexNet / training / floating point arithmetic / accuracy
Paper # CPSY2017-41
Date of Issue 2017-10-31 (CPSY)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC
Conference Date 2017/11/6(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Kumamoto-Kenminkouryukan Parea
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2017 -New Field of VLSI Design-
Chair Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII)
Vice Chair Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT)
Secretary Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.)
Assistant / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) DCNN Training with Short Bit Length Format Considering Loss of Trailing Digits
Sub Title (in English)
Keyword(1) Deep convolutional neural network (DCNN)
Keyword(2) AlexNet
Keyword(3) training
Keyword(4) floating point arithmetic
Keyword(5) accuracy
1st Author's Name Shin-ichi O'uchi
1st Author's Affiliation National Institute of AIST(AIST)
2nd Author's Name Hiroshi Fuketa
2nd Author's Affiliation National Institute of AIST(AIST)
3rd Author's Name Ryousei Takano
3rd Author's Affiliation National Institute of AIST(AIST)
Date 2017-11-07
Paper # CPSY2017-41
Volume (vol) vol.117
Number (no) CPSY-278
Page pp.pp.7-12(CPSY),
#Pages 6
Date of Issue 2017-10-31 (CPSY)