| Presentation | 2017-11-06 An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction Daichi Yuruki, Satoshi Ohtake, Yoshiyuki Nakamura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Today, semiconductor technologies have developed and advance the integration density of LSI circuits. A technique which keeps quality of LSIs and reduces test cost is necessary. We have shown that test cost reduction is possible by using machine learning techniques such as cluster analysis and support vector machine (SVM) for this problem. When performing discrimination by SVM, it is necessary to determine a threshold value for discriminating between good products and defective products. Since the appropriate threshold value fluctuates depending on data to be discriminated and discriminators, determination of an appropriate discriminator to be applied to the data and its discrimination threshold becomes an issue. In this paper, we propose a method to determine an optimal discriminator using SVM for this problem: apply the discrimination target data to a prior discriminator which is proposed in this paper, and select the discriminator that works effectively with a specific threshold value by using the distribution characteristic of the probability of good products. The effectiveness of the proposed method is evaluated by experiments using industrial test data. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Data mining / support vector machine / discriminant analysis / LSI testing |
| Paper # | VLD2017-36,DC2017-42 |
| Date of Issue | 2017-10-30 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2017/11/6(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto-Kenminkouryukan Parea |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.) |
| Assistant | / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction |
| Sub Title (in English) | |
| Keyword(1) | Data mining |
| Keyword(2) | support vector machine |
| Keyword(3) | discriminant analysis |
| Keyword(4) | LSI testing |
| 1st Author's Name | Daichi Yuruki |
| 1st Author's Affiliation | Oita University(Oita Univ) |
| 2nd Author's Name | Satoshi Ohtake |
| 2nd Author's Affiliation | Oita University(Oita Univ) |
| 3rd Author's Name | Yoshiyuki Nakamura |
| 3rd Author's Affiliation | Renesas Electronics Corporation(Renesas Electronics) |
| Date | 2017-11-06 |
| Paper # | VLD2017-36,DC2017-42 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-273,DC-274 |
| Page | pp.pp.55-60(VLD), pp.55-60(DC), |
| #Pages | 6 |
| Date of Issue | 2017-10-30 (VLD, DC) |