| Presentation | 2017-11-06 A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the increase in test costs for very large scale integrated circuits (VLSI). Especially DFT methods to reduce the number of test patterns at register transfer level (RTL) are required for the adaptability of traditional VLSI design flows and the reduction of time to search DFT locations. In this paper, we propose a DFT method at RTL to enable hardware elements to be concurrently tested with as small number of test patterns as possible in scan testing. The proposed method enhances the effectiveness of test compaction by enable efficient concurrent testing for hardware elements based on controller augmentation. Experimental results on high-level benchmark circuits show that our proposed method reduced the number of test patterns by 33.47% with 7.12 % area overhead on average. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | test register assignment / design for testability / controller augmentation / invalid test states / test scheduling |
| Paper # | VLD2017-37,DC2017-43 |
| Date of Issue | 2017-10-30 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2017/11/6(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto-Kenminkouryukan Parea |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.) |
| Assistant | / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation |
| Sub Title (in English) | |
| Keyword(1) | test register assignment |
| Keyword(2) | design for testability |
| Keyword(3) | controller augmentation |
| Keyword(4) | invalid test states |
| Keyword(5) | test scheduling |
| 1st Author's Name | Shun Takeda |
| 1st Author's Affiliation | Nihon University(Nihon Univ) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University(Nihon Univ) |
| 3rd Author's Name | Hiroshi Yamazaki |
| 3rd Author's Affiliation | Nihon University(Nihon Univ) |
| 4th Author's Name | Masayoshi Yoshimura |
| 4th Author's Affiliation | Kyoto Sangyo University(Kyoto Sangyo Univ) |
| Date | 2017-11-06 |
| Paper # | VLD2017-37,DC2017-43 |
| Volume (vol) | vol.117 |
| Number (no) | VLD-273,DC-274 |
| Page | pp.pp.61-66(VLD), pp.61-66(DC), |
| #Pages | 6 |
| Date of Issue | 2017-10-30 (VLD, DC) |