| Presentation | 2017-11-10 [Invited Talk] A SPICE-compatible SG-MONOS model for 28nm embedded flash macro design considering the parasitic resistance caused by trapped charges Risho Koh, Mitsuru Miyamori, Katsumi Tsuneno, Tetsuya Muta, Yoshiyuki Kawashima, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A SPICE-compatible model which reproduces the read current of split-gate MONOS (SG-MONOS) non-volatile memory cell has been developed for 28nm embedded flash macro design. The gap-resistance located between select-transistor and memory-transistor has been analyzed by using TCAD. It has been found that the trapped electrons located on top of the gap and near the gap significantly affects the parasitic resistance in the gap region and its vicinity, and It has been also found that the electric potential dependence on the select-gate voltage is weak at the gap region and its vicinity. Based on the result, a spice-compatible model in which the gap-resistance is reproduced by a synthesis of variable resistance is proposed. In the model, every variable resistance is exponentially dependent on the select-gate voltage. Temperature dependence of gap-resistance is also included in the model. These model configurations make it possible to include the parasitic resistance which becomes significant in the miniaturized generation cell. The model exhibits excellent fitting accuracy on the read current of SG-MONOS. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SPICE / Model / Non-volatile memory / MONOS / Split-gate / flash |
| Paper # | SDM2017-71 |
| Date of Issue | 2017-11-02 (SDM) |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2017/11/9(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Process, Device, Circuit simulation, etc. |
| Chair | Tatsuya Kunikiyo(Renesas) |
| Vice Chair | Takahiro Shinada(Tohoku Univ.) |
| Secretary | Takahiro Shinada(Tohoku Univ.) |
| Assistant | Hiroya Ikeda(Shizuoka Univ.) / Tetsu Morooka(TOSHIBA MEMORY) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] A SPICE-compatible SG-MONOS model for 28nm embedded flash macro design considering the parasitic resistance caused by trapped charges |
| Sub Title (in English) | |
| Keyword(1) | SPICE |
| Keyword(2) | Model |
| Keyword(3) | Non-volatile memory |
| Keyword(4) | MONOS |
| Keyword(5) | Split-gate |
| Keyword(6) | flash |
| 1st Author's Name | Risho Koh |
| 1st Author's Affiliation | Renesas electronics(Renesas electronics) |
| 2nd Author's Name | Mitsuru Miyamori |
| 2nd Author's Affiliation | Renesas electronics(Renesas electronics) |
| 3rd Author's Name | Katsumi Tsuneno |
| 3rd Author's Affiliation | Renesas electronics(Renesas electronics) |
| 4th Author's Name | Tetsuya Muta |
| 4th Author's Affiliation | Renesas electronics(Renesas electronics) |
| 5th Author's Name | Yoshiyuki Kawashima |
| 5th Author's Affiliation | Renesas electronics(Renesas electronics) |
| Date | 2017-11-10 |
| Paper # | SDM2017-71 |
| Volume (vol) | vol.117 |
| Number (no) | SDM-290 |
| Page | pp.pp.53-58(SDM), |
| #Pages | 6 |
| Date of Issue | 2017-11-02 (SDM) |