| Presentation | 2017-11-08 ターンモデルベースの不規則網向けルーティング Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The number of computing nodes increases for both on-chip multi-core systems and supercomputers. Therefore, the network latency among the nodes is a critical issue for parallel applications. Recently researchers have shown that randomly connected networks can reduce the latency for both on-chip and off-chip systems. However, unlike regular networks, conventional routing methods induce deadlocks due to loops of channel dependencies on these networks. Recently proposed theorem that generalizes the turn model can achieve almost minimal and fully adaptive deadlock-free routing. However, it cannot be applied to irregular networks that contain diagonal links. In this work, we advance the theorem to apply it to arbitrary network topologies. We also provide a practical implementation based on the theorem. Experimental results show that it can improve network throughput by up to 138 % and can reduce the network latency by up to 2.9 % compared to conventional routing methods. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Interconnection Network / Deadlock-free Routing / High Performance Computing / Irregular Networks / Virtual Channels |
| Paper # | CPSY2017-44 |
| Date of Issue | 2017-10-31 (CPSY) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2017/11/6(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto-Kenminkouryukan Parea |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
| Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Michiko Inoue(NAIST) / Koji Nakano(Hiroshima Univ.) / Masato Motomura(Hokkaido Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Kiyoharu Hamaguchi(Shimane Univ.) / 渡辺 晴美(東海大) / Masahiro Goshima(NII) |
| Vice Chair | Noriyuki Minegishi(Mitsubishi Electric) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) / Mayumi Takeyama(Kitami Inst. of Tech.) / Makoto Nagata(Kobe Univ.) / Kazuya Kodama(NII) / Hideaki Kimata(NTT) |
| Secretary | Noriyuki Minegishi(Hiroshima City Univ.) / Satoshi Fukumoto(NTT) / Hidetsugu Irie(Kyoto Sangyo Univ.) / Takashi Miyoshi(Tokyo Inst. of Tech.) / Yuichiro Shibata(Utsunomiya Univ.) / Kentaro Sano(Hokkaido Univ.) / Mayumi Takeyama(Hiroshima City Univ.) / Makoto Nagata(e-trees.Japan) / Kazuya Kodama(Nihon Univ.) / Hideaki Kimata(Toyohashi Univ. of Tech.) / (Univ. of Tokyo) / (Panasonic) / (Nagoya Univ.) |
| Assistant | / Masayuki Arai(Nihon Univ.) / Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) / Yuichi Akage(NTT) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Yasutaka Matsuo(NHK) / Kazuya Hayase(NTT) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN-ONLY |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | |
| Sub Title (in English) | |
| Keyword(1) | Interconnection Network |
| Keyword(2) | Deadlock-free Routing |
| Keyword(3) | High Performance Computing |
| Keyword(4) | Irregular Networks |
| Keyword(5) | Virtual Channels |
| 1st Author's Name | Ryuta Kawano |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Ryota Yasudo |
| 2nd Author's Affiliation | Keio University(Keio Univ.) |
| 3rd Author's Name | Hiroki Matsutani |
| 3rd Author's Affiliation | Keio University(Keio Univ.) |
| 4th Author's Name | Michihiro Koibuchi |
| 4th Author's Affiliation | National Institute of Informatics(NII) |
| 5th Author's Name | Hideharu Amano |
| 5th Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2017-11-08 |
| Paper # | CPSY2017-44 |
| Volume (vol) | vol.117 |
| Number (no) | CPSY-278 |
| Page | pp.pp.23-28(CPSY), |
| #Pages | 6 |
| Date of Issue | 2017-10-31 (CPSY) |