| Presentation | 2017-09-26 A case study of High-level Synthesis Using Higher-order Function on Functional Language Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forced design methodologies and tools to raise the level of design abstraction beyond register transfer level. The most popular approach has been to develop tools that use procedual languages in a C-like language. However, coarse-grain parallelism from a C program cannot be easily extracted, hence some tools use explicitly parallel languages to design hardware. But, all these tools rely on the programmer to correctly parallelize the application and perform optimizations which often needs hardware design knowledge. In this work, we propose a high-level synthesis tool for FPGAs using DSL embedded in Haskell as the design language and search program for degree of parallelism. Haskell is a pure functional language and better fit for hardware design. We implemented higher-order functions such as map, zipWith and reduce in our DSL, which allows us to automatically extract parallelism in the design. The evaluation results show that our proposed implementation achieves 3.00 and 4.96 times speed-up in two benchmarks, array addition and summation of array, respectively, relative to a C-like language design. Moreover, we also confirme that it is consistent with the result of search program for degree of parallelism. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-level Synthesis / Functional Language / FPGA |
| Paper # | RECONF2017-35 |
| Date of Issue | 2017-09-18 (RECONF) |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2017/9/25(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | DWANGO Co., Ltd. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Chair | Masato Motomura(Hokkaido Univ.) |
| Vice Chair | Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) |
| Secretary | Yuichiro Shibata(Hiroshima City Univ.) / Kentaro Sano(e-trees.Japan) |
| Assistant | Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A case study of High-level Synthesis Using Higher-order Function on Functional Language |
| Sub Title (in English) | |
| Keyword(1) | High-level Synthesis |
| Keyword(2) | Functional Language |
| Keyword(3) | FPGA |
| 1st Author's Name | Takuya Teraoka |
| 1st Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 2nd Author's Name | Morihiro Kuga |
| 2nd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 5th Author's Name | Toshinori Sueyoshi |
| 5th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| Date | 2017-09-26 |
| Paper # | RECONF2017-35 |
| Volume (vol) | vol.117 |
| Number (no) | RECONF-221 |
| Page | pp.pp.75-80(RECONF), |
| #Pages | 6 |
| Date of Issue | 2017-09-18 (RECONF) |