| Presentation | 2017-09-26 Implementing RISC-V with a Python-Based High-Level Synthesis Compiler Ryouzaburo Suzuki, Hiroaki Kataoka, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | During the last decade, the environment of field-programmable gate array (FPGA) development has changed rapidly, and the complexity of applications is increasing every year. As a result, design methodologies with higher levels of abstraction are required for both synthesis and verification processes, and high-level synthesis (HLS) compilers have become essential to support such methodologies. We have already shown a design methodology with a high level of abstraction that uses Polyphony, which is a Python-based HLS compiler. In this paper, we present different scenarios written in a Python-based HLS language for implementing RISC-V. By using workers, queues and ports of a message-passing mechanism, an HLS compiler with no control over clock-level timing can simulate and evaluate a pipelining architecture such as RISC-V. This high-abstraction-level methodology results in expedited development and enhanced readability. Designers can then develop complex systems with FPGAs by building processors in an HLS language that has no inherent expressions to control clock-level timing. What all this suggests is that, with further optimized compilers, building high-performance systems for stream-processing in an HLS language may be achieved in the near future. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Python / HLS / RISC-V |
| Paper # | RECONF2017-36 |
| Date of Issue | 2017-09-18 (RECONF) |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2017/9/25(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | DWANGO Co., Ltd. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Chair | Masato Motomura(Hokkaido Univ.) |
| Vice Chair | Yuichiro Shibata(Nagasaki Univ.) / Kentaro Sano(Tohoku Univ.) |
| Secretary | Yuichiro Shibata(Hiroshima City Univ.) / Kentaro Sano(e-trees.Japan) |
| Assistant | Yuuki Kobayashi(NEC) / Hiroki Nakahara(Tokyo Inst. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementing RISC-V with a Python-Based High-Level Synthesis Compiler |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Python |
| Keyword(3) | HLS |
| Keyword(4) | RISC-V |
| 1st Author's Name | Ryouzaburo Suzuki |
| 1st Author's Affiliation | Sinby Corporation(Sinby) |
| 2nd Author's Name | Hiroaki Kataoka |
| 2nd Author's Affiliation | Sinby Corporation(Sinby) |
| Date | 2017-09-26 |
| Paper # | RECONF2017-36 |
| Volume (vol) | vol.117 |
| Number (no) | RECONF-221 |
| Page | pp.pp.81-86(RECONF), |
| #Pages | 6 |
| Date of Issue | 2017-09-18 (RECONF) |