| Presentation | 2017-08-01 Parallel Programming of Non-volatile Power-up States of SRAM Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A technique for using an ordinary SRAM array for programmable and readable non-volatile (NV) memory is proposed. Parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the SRAM array. On ramping up power supply voltage, the NV data will be automatically recalled into the SRAM array. Successful 2kbit NV writing is demonstrated using a device-matrix-array (DMA) TEG fabricated by 0.18μm technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | non-volatile memory / one-time programmable memory / CMOS / SRAM |
| Paper # | SDM2017-38,ICD2017-26 |
| Date of Issue | 2017-07-24 (SDM, ICD) |
| Conference Information | |
| Committee | SDM / ICD / ITE-IST |
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| Conference Date | 2017/7/31(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido-Univ. Multimedia Education Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low voltage/low power techniques, novel devices, circuits, and applications |
| Chair | Tatsuya Kunikiyo(Renesas) / Hideto Hidaka(Renesas) / Shigetoshi Sugawa(Tohoku Univ.) |
| Vice Chair | Takahiro Shinada(Tohoku Univ.) / Makoto Nagata(Kobe Univ.) / Takayuki Hamamoto(Tokyo University of Science) / Hiroshi Ohtake(NHK) |
| Secretary | Takahiro Shinada(Tohoku Univ.) / Makoto Nagata(Renesas) / Takayuki Hamamoto(Univ. of Tokyo) / Hiroshi Ohtake(Panasonic) |
| Assistant | Hiroya Ikeda(Shizuoka Univ.) / Tetsu Morooka(TOSHIBA MEMORY) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials / Technical Committee on Integrated Circuits and Devices / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Parallel Programming of Non-volatile Power-up States of SRAM |
| Sub Title (in English) | |
| Keyword(1) | non-volatile memory |
| Keyword(2) | one-time programmable memory |
| Keyword(3) | CMOS |
| Keyword(4) | SRAM |
| 1st Author's Name | Tomoko Mizutani |
| 1st Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 2nd Author's Name | Kiyoshi Takeuchi |
| 2nd Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 3rd Author's Name | Takuya Saraya |
| 3rd Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 4th Author's Name | Hirofumi Shinohara |
| 4th Author's Affiliation | Waseda University(Waseda Univ.) |
| 5th Author's Name | Masaharu Kobayashi |
| 5th Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 6th Author's Name | Toshiro Hiramoto |
| 6th Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| Date | 2017-08-01 |
| Paper # | SDM2017-38,ICD2017-26 |
| Volume (vol) | vol.117 |
| Number (no) | SDM-166,ICD-167 |
| Page | pp.pp.49-54(SDM), pp.49-54(ICD), |
| #Pages | 6 |
| Date of Issue | 2017-07-24 (SDM, ICD) |