| Presentation | 2017-07-31 TCAD Simulation of C-TFET Circuit with Drain Offset Structure Hidehiro Asai, Takahiro Mori, Junich Hattori, Koichi Fukuda, Kazuhiko Endo, Takashi Matsukawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have performed TCAD simulation for a ring oscillator composed of complementary Tunnel Field Effect Transistors (C-TFETs), and analyzed the effect of drain-offset structure on the circuit characteristics. The drain-offset structure lowers the OFF current from the drain edge, and this unable us to shrink the gate length of the TFETs. Furthermore, the reduction of gate-drain capacitance (CGD) enhances the oscillation frequency of the ring oscillator. The enhancement effect of frequency by the drain-offset structure is strongly related to the unique dependence of CGD on the drain voltage, and affected by the operation voltage of the ring oscillator. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Tunnel FET / Ring oscillator / Drain offset |
| Paper # | SDM2017-35,ICD2017-23 |
| Date of Issue | 2017-07-24 (SDM, ICD) |
| Conference Information | |
| Committee | SDM / ICD / ITE-IST |
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| Conference Date | 2017/7/31(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido-Univ. Multimedia Education Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low voltage/low power techniques, novel devices, circuits, and applications |
| Chair | Tatsuya Kunikiyo(Renesas) / Hideto Hidaka(Renesas) / Shigetoshi Sugawa(Tohoku Univ.) |
| Vice Chair | Takahiro Shinada(Tohoku Univ.) / Makoto Nagata(Kobe Univ.) / Takayuki Hamamoto(Tokyo University of Science) / Hiroshi Ohtake(NHK) |
| Secretary | Takahiro Shinada(Tohoku Univ.) / Makoto Nagata(Renesas) / Takayuki Hamamoto(Univ. of Tokyo) / Hiroshi Ohtake(Panasonic) |
| Assistant | Hiroya Ikeda(Shizuoka Univ.) / Tetsu Morooka(TOSHIBA MEMORY) / Masanori Natsui(Tohoku Univ.) / Masatoshi Tsuge(Socionext) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials / Technical Committee on Integrated Circuits and Devices / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | TCAD Simulation of C-TFET Circuit with Drain Offset Structure |
| Sub Title (in English) | |
| Keyword(1) | Tunnel FET |
| Keyword(2) | Ring oscillator |
| Keyword(3) | Drain offset |
| 1st Author's Name | Hidehiro Asai |
| 1st Author's Affiliation | National Institute of Advanced Industrial Science and Technology(AIST) |
| 2nd Author's Name | Takahiro Mori |
| 2nd Author's Affiliation | National Institute of Advanced Industrial Science and Technology(AIST) |
| 3rd Author's Name | Junich Hattori |
| 3rd Author's Affiliation | National Institute of Advanced Industrial Science and Technology(AIST) |
| 4th Author's Name | Koichi Fukuda |
| 4th Author's Affiliation | National Institute of Advanced Industrial Science and Technology(AIST) |
| 5th Author's Name | Kazuhiko Endo |
| 5th Author's Affiliation | National Institute of Advanced Industrial Science and Technology(AIST) |
| 6th Author's Name | Takashi Matsukawa |
| 6th Author's Affiliation | National Institute of Advanced Industrial Science and Technology(AIST) |
| Date | 2017-07-31 |
| Paper # | SDM2017-35,ICD2017-23 |
| Volume (vol) | vol.117 |
| Number (no) | SDM-166,ICD-167 |
| Page | pp.pp.21-24(SDM), pp.21-24(ICD), |
| #Pages | 4 |
| Date of Issue | 2017-07-24 (SDM, ICD) |