| Presentation | 2017-07-27 Reducing Number of Slots in Circuit-switched Network for Parallel Computers Yao Hu, Tomohiro Kudoh, Michihiro Koibuchi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Network congestion usually happens in supercomputers and datacenter networks. This would lead to increased communication time. In this report, we propose a TDM-based circuit switching network to avoid the network congestion. Each switch in the network caches (reads) incoming data in an input slot (buffer) and later transfers (writes) it to an output slot (buffer). The connection between the input slot and the output slot is established beforehand. The read and write operations on input and output slots are not synchronized but with the same frequency. Thus the whole network guarantees the lowest bandwidth and the largest latency for each communication node pair. The number of total slots for every switch is a direct factor to affect the end-to-end latency. To reduce the required number of slots in the network, we propose a method to automatically generate an interconnection topology according to a given communication pattern and maximum switch degree. Evaluation results show that the number of network resources can be reduced by the proposed topology generator when compared to a 2-D mesh or torus. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | datacenter networkcircuit switchinginterconnection networktime division multiplexing (TDM) |
| Paper # | CPSY2017-26 |
| Date of Issue | 2017-07-19 (CPSY) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2017/7/26(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Akita Atorion-Building (Akita) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Parallel, Distributed and Cooperative Processing |
| Chair | Koji Nakano(Hiroshima Univ.) / Michiko Inoue(NAIST) |
| Vice Chair | Hidetsugu Irie(Univ. of Tokyo) / Takashi Miyoshi(Fujitsu) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Hidetsugu Irie(Utsunomiya Univ.) / Takashi Miyoshi(Hokkaido Univ.) / Satoshi Fukumoto(Kyoto Sangyo Univ.) / (Tokyo Inst. of Tech.) |
| Assistant | Yasuaki Ito(Hiroshima Univ.) / Tomoaki Tsumura(Nagoya Inst. of Tech.) / Masayuki Arai(Nihon Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reducing Number of Slots in Circuit-switched Network for Parallel Computers |
| Sub Title (in English) | |
| Keyword(1) | datacenter networkcircuit switchinginterconnection networktime division multiplexing (TDM) |
| 1st Author's Name | Yao Hu |
| 1st Author's Affiliation | National Institute of Informatics(NII) |
| 2nd Author's Name | Tomohiro Kudoh |
| 2nd Author's Affiliation | University of Tokyo(Univ. of Tokyo) |
| 3rd Author's Name | Michihiro Koibuchi |
| 3rd Author's Affiliation | National Institute of Informatics(NII) |
| Date | 2017-07-27 |
| Paper # | CPSY2017-26 |
| Volume (vol) | vol.117 |
| Number (no) | CPSY-153 |
| Page | pp.pp.111-116(CPSY), |
| #Pages | 6 |
| Date of Issue | 2017-07-19 (CPSY) |