| Presentation | 2017-06-20 SAT model sampling for test pattern generation considering signal transition activities Yusuke Matsunaga, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a test pattern generation method with considering signal transition activities using a SAT solver. A simple SAT based test pattern generation method can only find a single pattern per a fault, which does not consider the signal transition activities. The proposed method employs a randam sampling algorithm for SAT problem, which adds randomly generated constraints to the original problem. The proposed method can generate arbitary number of test patterns for one fault, so that the user can select the best one among those patterns with respect to signal transition activities or power consumption. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | test pattern generation / signal transition activity / SAT / random sampling |
| Paper # | CAS2017-21,VLD2017-24,SIP2017-45,MSS2017-21 |
| Date of Issue | 2017-06-12 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | SIP / CAS / MSS / VLD |
|---|---|
| Conference Date | 2017/6/19(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Niigata University, Ikarashi Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Masahiro Okuda(Univ. of Kitakyushu) / Mitsuru Hiraki(Renesas) / Morikazu Nakamura(Univ. of Ryukyus) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shogo Muramatsu(Niigata Univ.) / Naoyuki Aikawa(TUS) / Hideaki Okazaki(Shonan Inst. of Tech.) / Shigemasa Takai(Osaka Univ.) / Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Shogo Muramatsu(Chiba Inst. of Tech.) / Naoyuki Aikawa(Takushoku Univ.) / Hideaki Okazaki(Renesas) / Shigemasa Takai(Shonan Inst. of Tech.) / Noriyuki Minegishi(Toshiba) |
| Assistant | Masayoshi Nakamoto(Hiroshima Univ.ひろ) / Yohei Nakamura(Hitachi) / Hideki Kinjo(Okinawa Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Signal Processing / Technical Committee on Circuits and Systems / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on VLSI Design Technologies |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | SAT model sampling for test pattern generation considering signal transition activities |
| Sub Title (in English) | |
| Keyword(1) | test pattern generation |
| Keyword(2) | signal transition activity |
| Keyword(3) | SAT |
| Keyword(4) | random sampling |
| 1st Author's Name | Yusuke Matsunaga |
| 1st Author's Affiliation | Kyushu University(Kyushu Univ.) |
| Date | 2017-06-20 |
| Paper # | CAS2017-21,VLD2017-24,SIP2017-45,MSS2017-21 |
| Volume (vol) | vol.117 |
| Number (no) | CAS-96,VLD-97,SIP-98,MSS-99 |
| Page | pp.pp.107-112(CAS), pp.107-112(VLD), pp.107-112(SIP), pp.107-112(MSS), |
| #Pages | 6 |
| Date of Issue | 2017-06-12 (CAS, VLD, SIP, MSS) |