| Presentation | 2017-06-19 Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation Ryosuke Koike, Takashi Imagawa, Roberto Yusi Omaki, Hiroyuki Ochi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we describe a Selectable Grained Reconfigurable Architecture (SGRA) in which each Configurable Logic Block can be configured to operate in either fine-grained or coarse-grained mode. Compared with the Mixed Grained Reconfigurable Architecture (MGRA), which has a fixed ratio of fine- and coarse-grained operation blocks and a heterogeneous floorplan, SGRA offers greater flexibility in the mapping and placement of functional units, thus reducing wasted wiring and improving the critical path delay. We also present an automated design flow for SGRA that is developed by customizing the Verilog-to-Routing (VTR) platform. Experimental results demonstrate that SGRA achieves, on average, a 13% reduction in circuit area over MGRA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA architecture / Homogeneous array / Technology-mapping using subgraph matching method |
| Paper # | CAS2017-5,VLD2017-8,SIP2017-29,MSS2017-5 |
| Date of Issue | 2017-06-12 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | SIP / CAS / MSS / VLD |
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| Conference Date | 2017/6/19(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Niigata University, Ikarashi Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Masahiro Okuda(Univ. of Kitakyushu) / Mitsuru Hiraki(Renesas) / Morikazu Nakamura(Univ. of Ryukyus) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shogo Muramatsu(Niigata Univ.) / Naoyuki Aikawa(TUS) / Hideaki Okazaki(Shonan Inst. of Tech.) / Shigemasa Takai(Osaka Univ.) / Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Shogo Muramatsu(Chiba Inst. of Tech.) / Naoyuki Aikawa(Takushoku Univ.) / Hideaki Okazaki(Renesas) / Shigemasa Takai(Shonan Inst. of Tech.) / Noriyuki Minegishi(Toshiba) |
| Assistant | Masayoshi Nakamoto(Hiroshima Univ.ひろ) / Yohei Nakamura(Hitachi) / Hideki Kinjo(Okinawa Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Signal Processing / Technical Committee on Circuits and Systems / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on VLSI Design Technologies |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation |
| Sub Title (in English) | |
| Keyword(1) | FPGA architecture |
| Keyword(2) | Homogeneous array |
| Keyword(3) | Technology-mapping using subgraph matching method |
| 1st Author's Name | Ryosuke Koike |
| 1st Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 2nd Author's Name | Takashi Imagawa |
| 2nd Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 3rd Author's Name | Roberto Yusi Omaki |
| 3rd Author's Affiliation | Synthesis Corporation(Synthesis) |
| 4th Author's Name | Hiroyuki Ochi |
| 4th Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| Date | 2017-06-19 |
| Paper # | CAS2017-5,VLD2017-8,SIP2017-29,MSS2017-5 |
| Volume (vol) | vol.117 |
| Number (no) | CAS-96,VLD-97,SIP-98,MSS-99 |
| Page | pp.pp.25-30(CAS), pp.25-30(VLD), pp.25-30(SIP), pp.25-30(MSS), |
| #Pages | 6 |
| Date of Issue | 2017-06-12 (CAS, VLD, SIP, MSS) |