| Presentation | 2017-06-20 Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit Yuta Ukon, Shimpei Sato, Atsushi Takahashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | There are a lot of high load processing that is not required high accuracy at the data center. An approximate computing circuit is effective for processing at high speed and saving resources. In this research, we aim to realize an approximate computing circuit with the approach that a general-synchronous circuit which allowed variable latency continues processing even if a timing error occurs in some FFs. In the case of processing at a high-speed with a complete guarantee of a variable latency circuit, the circuit area increases due to increase replaced FFs and inserted delay elements. On the other hand, in the case of processing by allowing to occur timing errors, it may be possible to reduce replaced FFs and inserted delay elements and to process at a high speed. Therefore, according to allow error, it is necessary to determine a number of FFs to be replaced and a number of delay elements to be inserted. In this paper, we investigate a circuit area and processing performance for the delay amount inserted, and output accuracy for a number of replaced FFs by a gate level simulation for an adder. As the results, by inserting delay elements on a circuit, effective clock period is reduced by 34.92% at maximum, while a circuit area is increased by 145.83%. We also confirmed that approximate computing with decreased a maximum error and an average error can be performed by allowing only lower bit FFs to occur errors. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | General-synchronous circuit / Error detection and correction method / Variable latency / Approximate computing |
| Paper # | CAS2017-23,VLD2017-26,SIP2017-47,MSS2017-23 |
| Date of Issue | 2017-06-12 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | SIP / CAS / MSS / VLD |
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| Conference Date | 2017/6/19(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Niigata University, Ikarashi Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Masahiro Okuda(Univ. of Kitakyushu) / Mitsuru Hiraki(Renesas) / Morikazu Nakamura(Univ. of Ryukyus) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shogo Muramatsu(Niigata Univ.) / Naoyuki Aikawa(TUS) / Hideaki Okazaki(Shonan Inst. of Tech.) / Shigemasa Takai(Osaka Univ.) / Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Shogo Muramatsu(Chiba Inst. of Tech.) / Naoyuki Aikawa(Takushoku Univ.) / Hideaki Okazaki(Renesas) / Shigemasa Takai(Shonan Inst. of Tech.) / Noriyuki Minegishi(Toshiba) |
| Assistant | Masayoshi Nakamoto(Hiroshima Univ.ひろ) / Yohei Nakamura(Hitachi) / Hideki Kinjo(Okinawa Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Signal Processing / Technical Committee on Circuits and Systems / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit |
| Sub Title (in English) | |
| Keyword(1) | General-synchronous circuit |
| Keyword(2) | Error detection and correction method |
| Keyword(3) | Variable latency |
| Keyword(4) | Approximate computing |
| 1st Author's Name | Yuta Ukon |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Inst. of Tech.) |
| 2nd Author's Name | Shimpei Sato |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Inst. of Tech.) |
| 3rd Author's Name | Atsushi Takahashi |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Tokyo Inst. of Tech.) |
| Date | 2017-06-20 |
| Paper # | CAS2017-23,VLD2017-26,SIP2017-47,MSS2017-23 |
| Volume (vol) | vol.117 |
| Number (no) | CAS-96,VLD-97,SIP-98,MSS-99 |
| Page | pp.pp.119-124(CAS), pp.119-124(VLD), pp.119-124(SIP), pp.119-124(MSS), |
| #Pages | 6 |
| Date of Issue | 2017-06-12 (CAS, VLD, SIP, MSS) |