| Presentation | 2017-06-19 Placement Algorithm for Mixed-Grained Reconfigurable Architecture with Dedicated Carry Chain Koki Honda, Takashi Imagawa, Hiroyuki Ochi, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a placement algorithm using analytical placement (AP) and low-temperature simulated annealing (SA) for mixed-grained reconfigurable architecture (MGRA) with dedicated carry chains. The target MGRAs are assumed to have fine-grained blocks with dedicated carry chains to implement high-speed adders/subtracters and coarse-grained blocks to implement complicated arithmetic operations. Although this architecture is expected to enhance the performance of the implemented circuit, placement using simple pair-swap-based SA often converges to a local optimum. The proposed algorithm uses AP to determine an initial placement for SA. The AP explores an appropriate placement of coarse-grained blocks and adders/subtracters consisting of fine-grained blocks and dedicated carry chains. On the other hand, SA is mainly used to determine optimal placement of the remaining fine-grained blocks. The evaluations show that the proposed algorithm reduces the placement cost, critical path delay, and runtime by 18.4%, 6.0%, and 67.6% on average, respectively, over the Versatile Place and Route (VPR). The benchmark includes circuits consisting of only fine-grained logic. Hence, the proposed algorithm is expected to improve the placement quality for a wide range of application circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | analytical placement / low-temperature simulated annealing / initial placement / initial temperature |
| Paper # | CAS2017-4,VLD2017-7,SIP2017-28,MSS2017-4 |
| Date of Issue | 2017-06-12 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | SIP / CAS / MSS / VLD |
|---|---|
| Conference Date | 2017/6/19(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Niigata University, Ikarashi Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Masahiro Okuda(Univ. of Kitakyushu) / Mitsuru Hiraki(Renesas) / Morikazu Nakamura(Univ. of Ryukyus) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Vice Chair | Shogo Muramatsu(Niigata Univ.) / Naoyuki Aikawa(TUS) / Hideaki Okazaki(Shonan Inst. of Tech.) / Shigemasa Takai(Osaka Univ.) / Noriyuki Minegishi(Mitsubishi Electric) |
| Secretary | Shogo Muramatsu(Chiba Inst. of Tech.) / Naoyuki Aikawa(Takushoku Univ.) / Hideaki Okazaki(Renesas) / Shigemasa Takai(Shonan Inst. of Tech.) / Noriyuki Minegishi(Toshiba) |
| Assistant | Masayoshi Nakamoto(Hiroshima Univ.ひろ) / Yohei Nakamura(Hitachi) / Hideki Kinjo(Okinawa Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Signal Processing / Technical Committee on Circuits and Systems / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on VLSI Design Technologies |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Placement Algorithm for Mixed-Grained Reconfigurable Architecture with Dedicated Carry Chain |
| Sub Title (in English) | |
| Keyword(1) | analytical placement |
| Keyword(2) | low-temperature simulated annealing |
| Keyword(3) | initial placement |
| Keyword(4) | initial temperature |
| 1st Author's Name | Koki Honda |
| 1st Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 2nd Author's Name | Takashi Imagawa |
| 2nd Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| 3rd Author's Name | Hiroyuki Ochi |
| 3rd Author's Affiliation | Ritsumeikan University(Ritsumeikan Univ.) |
| Date | 2017-06-19 |
| Paper # | CAS2017-4,VLD2017-7,SIP2017-28,MSS2017-4 |
| Volume (vol) | vol.117 |
| Number (no) | CAS-96,VLD-97,SIP-98,MSS-99 |
| Page | pp.pp.19-24(CAS), pp.19-24(VLD), pp.19-24(SIP), pp.19-24(MSS), |
| #Pages | 6 |
| Date of Issue | 2017-06-12 (CAS, VLD, SIP, MSS) |