| Presentation | 2017-05-22 A proposal of Bit Serial Arithmetic Units for Arbitrary Precision Tomonori Miura, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper,we propose a bit serial arithmetic unit for arbitrary precision.It calculates 1 digit ev- ery cycle from the most significant bit.And when necessary calculation precision is obtained,the calculation is ended.Therefore,there is no need to perform unnecessary calculation,and this may lead to the improvement of throughput and the reduction of power consumption.Also,since 1-bit width arithmetic unit is used without using a general 32-bit or 64-bit width one,the area is small.At first,we describe algorithms of four arithmetic operations that can calculate in arbitrary precision,and then we implemented it in Verilog HDL.Finally, using the MAC(Multiply-Accumulate) operation that is often used in digital signal processing,we evaluated throughput,power consumption and area. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Bit serial operation / Gray Code / Arbitrary Precision |
| Paper # | RECONF2017-8 |
| Date of Issue | 2017-05-15 (RECONF) |
| Conference Information | |
| Committee | RECONF / CPSY / DC / IPSJ-ARC |
|---|---|
| Conference Date | 2017/5/22(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | HotSPA2017: Reconfigurable System, Dependable Computing System, and General Topics |
| Chair | Minoru Watanabe(Shizuoka Univ.) / Yasuhiko Nakashima(NAIST) / Michiko Inoue(NAIST) |
| Vice Chair | Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Masato Motomura(Univ. of Tsukuba) / Yuichiro Shibata(Hiroshima City Univ.) / Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) / Satoshi Fukumoto(Kyoto Sangyo Univ.) / (Tokyo Inst. of Tech.) |
| Assistant | Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(Hokkaido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems / Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A proposal of Bit Serial Arithmetic Units for Arbitrary Precision |
| Sub Title (in English) | |
| Keyword(1) | Bit serial operation |
| Keyword(2) | Gray Code |
| Keyword(3) | Arbitrary Precision |
| 1st Author's Name | Tomonori Miura |
| 1st Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 2nd Author's Name | Motoki Amagasaki |
| 2nd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 3rd Author's Name | Masahiro Iida |
| 3rd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 4th Author's Name | Morihiro Kuga |
| 4th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 5th Author's Name | Toshinori Sueyoshi |
| 5th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| Date | 2017-05-22 |
| Paper # | RECONF2017-8 |
| Volume (vol) | vol.117 |
| Number (no) | RECONF-46 |
| Page | pp.pp.37-41(RECONF), |
| #Pages | 5 |
| Date of Issue | 2017-05-15 (RECONF) |