| Presentation | 2017-05-25 Development of Plasmonic Logical Circuit Using Multimode Interference Ryo Watanabe, Masashi Ota, Yudai Kikuchi, Tomohiro Hirano, Yuya Ishii, Mitsuo Fukuda, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Logic circuits using Surface Plasmon Polaritons(SPPs) as signal carriers have been attracting attentions. Recently, we have demonstrated all-SPP logical operation circuits composed of SiO2 patterns on a Au film. The circuits enable multi-input and multi-output operation using multi-mode interference of SPPs. In this paper, we have reduced the size of the SPP half adder by introducing a mode convertor and confirmed its operation analytically and experimentally. In addition, desired operation of the SPP phase adjustor has been confirmed at different wavelengths ranging from 1260nm to 1360nm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Surface Plasmon Polaritons / Multimode Interference / Half Adder / Photonic Device |
| Paper # | ED2017-20,CPM2017-6,SDM2017-14 |
| Date of Issue | 2017-05-18 (ED, CPM, SDM) |
| Conference Information | |
| Committee | SDM / ED / CPM |
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| Conference Date | 2017/5/25(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | VBL, Nagoya University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Tatsuya Kunikiyo(Renesas) / Koichi Maezawa(Univ. of Toyama) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takahiro Shinada(Tohoku Univ.) / Kunio Tsuda(Toshiba) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takahiro Shinada(Tohoku Univ.) / Kunio Tsuda(Renesas) / Fumihiko Hirose(JAIST) |
| Assistant | Hiroya Ikeda(Shizuoka Univ.) / Masataka Higashiwaki(NICT) / Toshiyuki Oishi(Saga Univ.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials / Technical Committee on Electron Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of Plasmonic Logical Circuit Using Multimode Interference |
| Sub Title (in English) | |
| Keyword(1) | Surface Plasmon Polaritons |
| Keyword(2) | Multimode Interference |
| Keyword(3) | Half Adder |
| Keyword(4) | Photonic Device |
| 1st Author's Name | Ryo Watanabe |
| 1st Author's Affiliation | Toyohashi University of Technology(TUT) |
| 2nd Author's Name | Masashi Ota |
| 2nd Author's Affiliation | Toyohashi University of Technology(TUT) |
| 3rd Author's Name | Yudai Kikuchi |
| 3rd Author's Affiliation | Toyohashi University of Technology(TUT) |
| 4th Author's Name | Tomohiro Hirano |
| 4th Author's Affiliation | Toyohashi University of Technology(TUT) |
| 5th Author's Name | Yuya Ishii |
| 5th Author's Affiliation | Toyohashi University of Technology(TUT) |
| 6th Author's Name | Mitsuo Fukuda |
| 6th Author's Affiliation | Toyohashi University of Technology(TUT) |
| Date | 2017-05-25 |
| Paper # | ED2017-20,CPM2017-6,SDM2017-14 |
| Volume (vol) | vol.117 |
| Number (no) | ED-58,CPM-59,SDM-60 |
| Page | pp.pp.29-32(ED), pp.29-32(CPM), pp.29-32(SDM), |
| #Pages | 4 |
| Date of Issue | 2017-05-18 (ED, CPM, SDM) |