Presentation 2017-04-20
Performance Evaluation of QoS Scheduling Architecture by the Coordination of Hardware and Software
Atsushi Kitada, Kazuto Nishimura, Hiroshi Tomonaga,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Recent improvements of CPU performance and multi-core/multi-thread processing are driving forward the network softwarization. But it’s still difficult to provide network functions with complicated algorithm like QoS scheduling at full wire rate in ultra-high speed interfaces such as 400 Gbit Ethernet by software. So we have proposed the QoS scheduling architecture by the coordination of hardware and software, rather than controlling everything by software. In this paper, we describe the further study for practical use of our architecture and the performance evaluation result by the prototype system, and we prove the effectiveness of our proposed architecture.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) QoS Scheduling / Softwarization / 400Gbit Ethernet / Coordination of Hardware and Software
Paper # CS2017-1
Date of Issue 2017-04-13 (CS)

Conference Information
Committee CS / CQ
Conference Date 2017/4/20(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Chitose Institute of Science and Technology
Topics (in Japanese) (See Japanese page)
Topics (in English) Network Serice, Service Quality, SDN (Software-Defined Networking), NFV (Network Functions. Virtualization), Network Virtualization, Cloud, Contents Delivery, etc
Chair Tetsuya Yokotani(Kanazawa Inst. of Tech.) / Kyoko Yamori(Asahi Univ.)
Vice Chair Hidenori Nakazato(Waseda Univ.) / Takanori Hayashi(NTT) / Hideyuki Shimonishi(NEC)
Secretary Hidenori Nakazato(NTT) / Takanori Hayashi(Kyushu Univ.) / Hideyuki Shimonishi(Osaka Univ.)
Assistant / Hirantha Abeysekera(NTT) / Norihiro Fukumoto(KDDI R&D Labs.)

Paper Information
Registration To Technical Committee on Communication Systems / Technical Committee on Communication Quality
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Performance Evaluation of QoS Scheduling Architecture by the Coordination of Hardware and Software
Sub Title (in English)
Keyword(1) QoS Scheduling
Keyword(2) Softwarization
Keyword(3) 400Gbit Ethernet
Keyword(4) Coordination of Hardware and Software
1st Author's Name Atsushi Kitada
1st Author's Affiliation Fujitsu Laboratories LTD.(Fujitsu Lab.)
2nd Author's Name Kazuto Nishimura
2nd Author's Affiliation Fujitsu Laboratories LTD.(Fujitsu Lab.)
3rd Author's Name Hiroshi Tomonaga
3rd Author's Affiliation Fujitsu Laboratories LTD.(Fujitsu Lab.)
Date 2017-04-20
Paper # CS2017-1
Volume (vol) vol.117
Number (no) CS-4
Page pp.pp.1-6(CS),
#Pages 6
Date of Issue 2017-04-13 (CS)