| Presentation | 2017-04-20 [Invited Talk] A 512Gb 3b/Cell Flash Memory on 64-Word-Line-Layer BiCS Technology Ryuji Yamashita, Sagar Magia, Tsutomu Higuchi, Kazuhide Yoneya, Toshio Yamamura, Hiroyuki Mizukoshi, Shingo Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A 512Gb 3b/cell flash has been developed on a 64-WL-layer BiCS technology. By using a four-block-EOC row decoding approach, row decoder area is reduced by 18%, which translates to a 1.3% die size reduction. With additional layout area reduction techniques, a 132mm2 die size and 3.88Gb/mm2 bit density have been achieved. SBL current sensing achieved a 64μs tR with an 8KB page size, which is 20% less than a conventional 16KB-page ABL. USP operation expanded the Vt window by 15%, which has significantly improved endurance and reliability. This work confirms that it is possible to meet market requirements for bit density, cost, performance, and reliability with this 3D-flash technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 3D-flash / BiCS / 64-word-line-layer / NAND flash memory / Non-volatile memory |
| Paper # | ICD2017-9 |
| Date of Issue | 2017-04-13 (ICD) |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2017/4/20(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Minoru Fujishima(Hiroshima Univ.) |
| Vice Chair | Hideto Hidaka(Renesas) |
| Secretary | Hideto Hidaka(Hiroshima Univ.) |
| Assistant | Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] A 512Gb 3b/Cell Flash Memory on 64-Word-Line-Layer BiCS Technology |
| Sub Title (in English) | |
| Keyword(1) | 3D-flash |
| Keyword(2) | BiCS |
| Keyword(3) | 64-word-line-layer |
| Keyword(4) | NAND flash memory |
| Keyword(5) | Non-volatile memory |
| 1st Author's Name | Ryuji Yamashita |
| 1st Author's Affiliation | Western Digital(WDC) |
| 2nd Author's Name | Sagar Magia |
| 2nd Author's Affiliation | Western Digital(WDC) |
| 3rd Author's Name | Tsutomu Higuchi |
| 3rd Author's Affiliation | Toshiba(Toshiba) |
| 4th Author's Name | Kazuhide Yoneya |
| 4th Author's Affiliation | Toshiba(Toshiba) |
| 5th Author's Name | Toshio Yamamura |
| 5th Author's Affiliation | Toshiba(Toshiba) |
| 6th Author's Name | Hiroyuki Mizukoshi |
| 6th Author's Affiliation | Western Digital(WDC) |
| 7th Author's Name | Shingo Zaitsu |
| 7th Author's Affiliation | Western Digital(WDC) |
| 8th Author's Name | Minoru Yamashita |
| 8th Author's Affiliation | Western Digital(WDC) |
| 9th Author's Name | Shunichi Toyama |
| 9th Author's Affiliation | Western Digital(WDC) |
| 10th Author's Name | Norihiro Kamae |
| 10th Author's Affiliation | Western Digital(WDC) |
| 11th Author's Name | Juan Lee |
| 11th Author's Affiliation | Western Digital(WDC) |
| 12th Author's Name | Shuo Chen |
| 12th Author's Affiliation | Western Digital(WDC) |
| 13th Author's Name | Jiawei Tao |
| 13th Author's Affiliation | Western Digital(WDC) |
| 14th Author's Name | William Mak |
| 14th Author's Affiliation | Western Digital(WDC) |
| 15th Author's Name | Xiaohua Zhang |
| 15th Author's Affiliation | Western Digital(WDC) |
| Date | 2017-04-20 |
| Paper # | ICD2017-9 |
| Volume (vol) | vol.117 |
| Number (no) | ICD-9 |
| Page | pp.pp.45-50(ICD), |
| #Pages | 6 |
| Date of Issue | 2017-04-13 (ICD) |