Presentation 2017-04-20
[Invited Lecture] First demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and beyond
Shibun Tsuda, Yoshiyuki Kawashima, Kenichiro Sonoda, Atsushi Yoshitomi, Tatsuyoshi Mihara, Shunichi Narumi, Masao Inoue, Seiji Muranaka, Takahiro Maruyama, Tomohiro Yamashita, Yasuo Yamaguchi, Digh Hisamoto,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the first time. Excellent subthreshold characteristics and small threshold-voltage variability owing to a Fin-structure are clarified. It is demonstrated that Fin top-corner effects are well suppressed by incremental step pulse programming for source side injection. Highly reliable data retention at 150 ºC after 250K program/erase cycles is confirmed for advanced automotive system applications.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) embedded Flash memory / split gate cell / MONOS / FinFET
Paper # ICD2017-7
Date of Issue 2017-04-13 (ICD)

Conference Information
Committee ICD
Conference Date 2017/4/20(2days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Minoru Fujishima(Hiroshima Univ.)
Vice Chair Hideto Hidaka(Renesas)
Secretary Hideto Hidaka(Hiroshima Univ.)
Assistant Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.)

Paper Information
Registration To Technical Committee on Integrated Circuits and Devices
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) [Invited Lecture] First demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and beyond
Sub Title (in English)
Keyword(1) embedded Flash memory
Keyword(2) split gate cell
Keyword(3) MONOS
Keyword(4) FinFET
1st Author's Name Shibun Tsuda
1st Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
2nd Author's Name Yoshiyuki Kawashima
2nd Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
3rd Author's Name Kenichiro Sonoda
3rd Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
4th Author's Name Atsushi Yoshitomi
4th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
5th Author's Name Tatsuyoshi Mihara
5th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
6th Author's Name Shunichi Narumi
6th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
7th Author's Name Masao Inoue
7th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
8th Author's Name Seiji Muranaka
8th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
9th Author's Name Takahiro Maruyama
9th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
10th Author's Name Tomohiro Yamashita
10th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
11th Author's Name Yasuo Yamaguchi
11th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
12th Author's Name Digh Hisamoto
12th Author's Affiliation Hitachi, Ltd(Hitachi)
Date 2017-04-20
Paper # ICD2017-7
Volume (vol) vol.117
Number (no) ICD-9
Page pp.pp.35-38(ICD),
#Pages 4
Date of Issue 2017-04-13 (ICD)