| Presentation | 2017-04-20 [Invited Talk] A 4Gb LPDDR2 STT-MRAM with Compact 9F2 1T1MTJ Cell and Hierarchical Bitline Architecture Kenji Tsuchida, Kwangmyoung Rho, Dongkeun Kim, Yutaka Shirai, Jihyae Bae, Tsuneo Inaba, Hiromi Noro, Hyunin Moon, Sungwoong Chung, Kazumasa Sunouchi, Jinwon Park, Kiseon Park, Akihito Yamamoto, Seoungju Chung, Hyeongon Kim, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The experimental 4-Gbit STT-MRAM with 9F2 1T1MTJ cell of 90nm by 90nm is presented. Hierarchical bit line architecture along with two circuit techniques contributes to total 44% reduction in bank height. In order to achieve the LPDDR2 compatible specifications even in a STT-MRAM, which has a smaller page-size than DRAM, the modifications for column command timing sequence are newly proposed. The chip size of 4Gbit STT-MRAM is 107.5 mm2, which is 14 times smaller than the previous best record. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | STT-MRAM / Perpendicular-TMR / Hierarchical Bitline Architecture / LPDDR2 Interface |
| Paper # | ICD2017-3 |
| Date of Issue | 2017-04-13 (ICD) |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2017/4/20(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Minoru Fujishima(Hiroshima Univ.) |
| Vice Chair | Hideto Hidaka(Renesas) |
| Secretary | Hideto Hidaka(Hiroshima Univ.) |
| Assistant | Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] A 4Gb LPDDR2 STT-MRAM with Compact 9F2 1T1MTJ Cell and Hierarchical Bitline Architecture |
| Sub Title (in English) | |
| Keyword(1) | STT-MRAM |
| Keyword(2) | Perpendicular-TMR |
| Keyword(3) | Hierarchical Bitline Architecture |
| Keyword(4) | LPDDR2 Interface |
| 1st Author's Name | Kenji Tsuchida |
| 1st Author's Affiliation | Toshiba Corporation(Toshiba) |
| 2nd Author's Name | Kwangmyoung Rho |
| 2nd Author's Affiliation | SK hynix Semiconductor(SK hynix) |
| 3rd Author's Name | Dongkeun Kim |
| 3rd Author's Affiliation | SK hynix Semiconductor(SK hynix) |
| 4th Author's Name | Yutaka Shirai |
| 4th Author's Affiliation | Toshiba Corporation(Toshiba) |
| 5th Author's Name | Jihyae Bae |
| 5th Author's Affiliation | SK hynix Semiconductor(SK hynix) |
| 6th Author's Name | Tsuneo Inaba |
| 6th Author's Affiliation | Toshiba Corporation(Toshiba) |
| 7th Author's Name | Hiromi Noro |
| 7th Author's Affiliation | Toshiba Corporation(Toshiba) |
| 8th Author's Name | Hyunin Moon |
| 8th Author's Affiliation | SK hynix Semiconductor(SK hynix) |
| 9th Author's Name | Sungwoong Chung |
| 9th Author's Affiliation | SK hynix Semiconductor(SK hynix) |
| 10th Author's Name | Kazumasa Sunouchi |
| 10th Author's Affiliation | Toshiba Corporation(Toshiba) |
| 11th Author's Name | Jinwon Park |
| 11th Author's Affiliation | SK hynix Semiconductor(SK hynix) |
| 12th Author's Name | Kiseon Park |
| 12th Author's Affiliation | SK hynix Semiconductor(SK hynix) |
| 13th Author's Name | Akihito Yamamoto |
| 13th Author's Affiliation | Toshiba Corporation(Toshiba) |
| 14th Author's Name | Seoungju Chung |
| 14th Author's Affiliation | SK hynix Semiconductor(SK hynix) |
| 15th Author's Name | Hyeongon Kim |
| 15th Author's Affiliation | SK hynix Semiconductor(SK hynix) |
| Date | 2017-04-20 |
| Paper # | ICD2017-3 |
| Volume (vol) | vol.117 |
| Number (no) | ICD-9 |
| Page | pp.pp.11-16(ICD), |
| #Pages | 6 |
| Date of Issue | 2017-04-13 (ICD) |