| Presentation | 2017-03-02 Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing Shun Sugihara, Shimpei Sato, Atsushi Takahashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In printed circuit board, to meet requirements such as delay and noise, routing of each net is necessary to achieve its target length. In recent years, various routing methods have been proposed to achieve the target length of each net, andgood routing results are obtained, but a net with error remains. In this work, a route modification method to achieve the target length by correcting the wire length of error net without changing the wire length of the other nets is proposed. From the experiments, we found that our proposed method correctsalmost all of errors in the case of a pattern which the number of netsis not so much. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | printed circuit board / single layer / route modification |
| Paper # | VLD2016-114 |
| Date of Issue | 2017-02-22 (VLD) |
| Conference Information | |
| Committee | VLD |
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| Conference Date | 2017/3/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Takashi Takenana(NEC) |
| Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) |
| Secretary | Hiroyuki Ochi(Fujitsu Labs.) |
| Assistant | Parizy Matthieu(Fujitsu Labs.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing |
| Sub Title (in English) | |
| Keyword(1) | printed circuit board |
| Keyword(2) | single layer |
| Keyword(3) | route modification |
| 1st Author's Name | Shun Sugihara |
| 1st Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 2nd Author's Name | Shimpei Sato |
| 2nd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| 3rd Author's Name | Atsushi Takahashi |
| 3rd Author's Affiliation | Tokyo Institute of Technology(Tokyo Tech) |
| Date | 2017-03-02 |
| Paper # | VLD2016-114 |
| Volume (vol) | vol.116 |
| Number (no) | VLD-478 |
| Page | pp.pp.73-78(VLD), |
| #Pages | 6 |
| Date of Issue | 2017-02-22 (VLD) |