Presentation 2017-03-01
A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating
Masaru Kudo, Kimiyoshi Usami,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper describes a nonvolatile Flip-Flop (NVFF) circuit to implement Nonvolatile Power Gating. We proposed a new NVFF circuit for stable store operation. We show effectiveness of area and energy dissipation by comparing the proposed circuit with conventional NVFF. Additionally, we evaluate leakage energy dissipation by using simulation for microprocessor which applied NVFF.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Power Gating / Magnetic Tunnel Junction / Nonvolatile Flip-Flop / Low Power
Paper # VLD2016-103
Date of Issue 2017-02-22 (VLD)

Conference Information
Committee VLD
Conference Date 2017/3/1(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Okinawa Seinen Kaikan
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Takashi Takenana(NEC)
Vice Chair Hiroyuki Ochi(Ritsumeikan Univ.)
Secretary Hiroyuki Ochi(Fujitsu Labs.)
Assistant Parizy Matthieu(Fujitsu Labs.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating
Sub Title (in English)
Keyword(1) Power Gating
Keyword(2) Magnetic Tunnel Junction
Keyword(3) Nonvolatile Flip-Flop
Keyword(4) Low Power
1st Author's Name Masaru Kudo
1st Author's Affiliation Shibaura lnstitute of Technology(Shibaura Institute of Tech.)
2nd Author's Name Kimiyoshi Usami
2nd Author's Affiliation Shibaura lnstitute of Technology(Shibaura Institute of Tech.)
Date 2017-03-01
Paper # VLD2016-103
Volume (vol) vol.116
Number (no) VLD-478
Page pp.pp.7-12(VLD),
#Pages 6
Date of Issue 2017-02-22 (VLD)