Presentation 2017-03-02
Optimum Temperature Dependent Timing Skew for Temperature Aware Design
Makoto Soga, Mineo Kaneko,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Electric devices equipping LSIs are widely distributed everywhere on the earth and the space, and LSIs are demanded to operate continuously in various temperature environments. Moreover, low power technologies such as clock gating, power gating, DVFS, may cause a drastic change of chip temperature. In this report, considering temperature dependent signal delays in a combinatorial circuit and delay elements for intentional skews, the optimum skew schedule which maximizes the upper limit of the operating temperature is discussed. The proposed algorithm to compute the optimum temperature dependent skew has been derived from the observation of how the lower and upper limits of the operating temperature and determined in a circuit, and its correctness is verified theoretically.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Clock Skew / Temperature Dependency / Setup Constraint / Hold Constraint
Paper # VLD2016-119
Date of Issue 2017-02-22 (VLD)

Conference Information
Committee VLD
Conference Date 2017/3/1(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Okinawa Seinen Kaikan
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Takashi Takenana(NEC)
Vice Chair Hiroyuki Ochi(Ritsumeikan Univ.)
Secretary Hiroyuki Ochi(Fujitsu Labs.)
Assistant Parizy Matthieu(Fujitsu Labs.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Optimum Temperature Dependent Timing Skew for Temperature Aware Design
Sub Title (in English)
Keyword(1) Clock Skew
Keyword(2) Temperature Dependency
Keyword(3) Setup Constraint
Keyword(4) Hold Constraint
1st Author's Name Makoto Soga
1st Author's Affiliation Japan Advanced Institute of Science and Technology(JAIST)
2nd Author's Name Mineo Kaneko
2nd Author's Affiliation Japan Advanced Institute of Science and Technology(JAIST)
Date 2017-03-02
Paper # VLD2016-119
Volume (vol) vol.116
Number (no) VLD-478
Page pp.pp.91-96(VLD),
#Pages 6
Date of Issue 2017-02-22 (VLD)