| Presentation | 2017-03-10 Development and Trial Evaluation of CPU Simulator with Register-transfer level Micro-Operation Shinya Hara, Yoshiro Imai, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a new educational tool for Computer Architecture, which can provide simulation of assembly program code (instead of machine language), demonstration of several kinds of sample programs and visualization of register-transfer-level structure/behavior, namely micro-operation. Our educational tool for CPU simulation has been designed and implemented in Javascript language as Web service. Its users select simulation modes by micro step, by machine cycle and by automatic repetition of such cycles. So they can learn how a computer works graphically, recognize inner structure of CPU and understand micro-operation based behavior of CPU. Our Simulator has been also evaluated through some kinds of questionnaires by users/learners in classroom lectures. It is confirmed that the simulator has been very useful and effective to learn Computer Architecture and behavior/organization of CPU by means of its application. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Educational Visualization / Computer Simulation at Register-transfer level / e-Learning |
| Paper # | ET2016-113 |
| Date of Issue | 2017-03-03 (ET) |
| Conference Information | |
| Committee | ET |
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| Conference Date | 2017/3/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | National Institute of Technology, Niihama College |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | STEM (Science, Technology, Engineering and Mathematics) Education, etc. |
| Chair | Yukihiro Matsubara(Hiroshima City Univ.) |
| Vice Chair | Shoichi Nakamura(Fukushima Univ.) |
| Secretary | Shoichi Nakamura(Yamaguchi Univ.) |
| Assistant | Yuichiro Tateiwa(Nagoya Inst. of Tech.) / Yuuki Nakayama(Fukushima Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Educational Technology |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development and Trial Evaluation of CPU Simulator with Register-transfer level Micro-Operation |
| Sub Title (in English) | |
| Keyword(1) | Educational Visualization |
| Keyword(2) | Computer Simulation at Register-transfer level |
| Keyword(3) | e-Learning |
| Keyword(4) | |
| Keyword(5) | |
| 1st Author's Name | Shinya Hara |
| 1st Author's Affiliation | Kagawa University(Kagawa Univ.) |
| 2nd Author's Name | Yoshiro Imai |
| 2nd Author's Affiliation | Kagawa University(Kagawa Univ.) |
| Date | 2017-03-10 |
| Paper # | ET2016-113 |
| Volume (vol) | vol.116 |
| Number (no) | ET-517 |
| Page | pp.pp.111-116(ET), |
| #Pages | 6 |
| Date of Issue | 2017-03-03 (ET) |