| Presentation | 2017-01-30 [Invited Talk] Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Level Cache Yoichi Shiota, Hiroki Noguchi, Kazutaka Ikegami, Keiko Abe, Shinobu Fujita, Takayuki Nozaki, Shinji Yuasa, Yoshishige Suzuki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In future processing system, the memory capacity of last level cache (LLC) must be increased, because LLC needs to cover the widening memory-bandwidth gap between multiple CPUs and the external main memory. For this purpose, non-volatile ultra-large LLCs (UL3C) having more than 100 MB should come into use. Although UL3Cs implemented with embedded DRAM have become commercially available, their usage has been constrained by their high power consumption due to their high refresh rate. Non-volatile UL3C can save this wasted energy and enables higher performance per watt in CPU/memory systems. This report presents voltage-controlled MRAM (VCM) using fast read and write circuits to achieve high-speed, low-power, and non-volatile UL3C. Our proposed circuit utilizes unipolar characteristics of voltage-torque MTJ and its voltage effects. The energy barrier is controlled by applying pulsed biases. Simulation results indicated the proposed circuits can operate even with 10% process variability at 1-sigma of MTJ fabrication and reduce operation power. Our results have shown that the proposed VCM can be used for nonvolatile UL3C. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Voltage torque MRAM / MTJ / Low power / LLC |
| Paper # | SDM2016-135 |
| Date of Issue | 2017-01-23 (SDM) |
| Conference Information | |
| Committee | SDM |
|---|---|
| Conference Date | 2017/1/30(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Tatsuya Kunikiyo(Renesas) |
| Vice Chair | Takahiro Shinada(Tohoku Univ.) |
| Secretary | Takahiro Shinada(Tohoku Univ.) |
| Assistant | Hiroya Ikeda(Shizuoka Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Level Cache |
| Sub Title (in English) | |
| Keyword(1) | Voltage torque MRAM |
| Keyword(2) | MTJ |
| Keyword(3) | Low power |
| Keyword(4) | LLC |
| 1st Author's Name | Yoichi Shiota |
| 1st Author's Affiliation | The National Institute of Advanced Industrial Science and Technology(AIST) |
| 2nd Author's Name | Hiroki Noguchi |
| 2nd Author's Affiliation | Toshiba(Toshiba) |
| 3rd Author's Name | Kazutaka Ikegami |
| 3rd Author's Affiliation | Toshiba(Toshiba) |
| 4th Author's Name | Keiko Abe |
| 4th Author's Affiliation | Toshiba(Toshiba) |
| 5th Author's Name | Shinobu Fujita |
| 5th Author's Affiliation | Toshiba(Toshiba) |
| 6th Author's Name | Takayuki Nozaki |
| 6th Author's Affiliation | The National Institute of Advanced Industrial Science and Technology(AIST) |
| 7th Author's Name | Shinji Yuasa |
| 7th Author's Affiliation | The National Institute of Advanced Industrial Science and Technology(AIST) |
| 8th Author's Name | Yoshishige Suzuki |
| 8th Author's Affiliation | Osaka University(Osaka Univ.) |
| Date | 2017-01-30 |
| Paper # | SDM2016-135 |
| Volume (vol) | vol.116 |
| Number (no) | SDM-448 |
| Page | pp.pp.21-24(SDM), |
| #Pages | 4 |
| Date of Issue | 2017-01-23 (SDM) |