| Presentation | 2017-01-30 [Invited Talk] Fully Coupled 3-D Device Simulation of Negative Capacitance FinFETs for Sub 10 nm Integration Hiroyuki Ota, Tsutomu Ikegami, Junichi Hattori, Koichi Fukuda, Shinji Migita, Akira Toriumi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Subthreshold operation of negative capacitance FinFETs (NC-FinFETs) at sub 10 nm gate length are analyzed with a newly developed technology computer-aided design (TCAD) simulation. This simulation fully couples the Landau-Khalatnikov (L-K) equation with the physical equations for FinFETs in 3-D. It reveals an excellent immunity against short channel effects in NC-FinFETs owing to NC-enhancement by the gate-to-drain coupling, for the first time. NC-FinFETs with a gate length of 10 nm are projected to operate with more than 26 times energy-efficiency of conventional FinFETs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | ferroelectric / negative capacitance / technology computer-aided design / low power / subthreshold / steep |
| Paper # | SDM2016-133 |
| Date of Issue | 2017-01-23 (SDM) |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2017/1/30(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Tatsuya Kunikiyo(Renesas) |
| Vice Chair | Takahiro Shinada(Tohoku Univ.) |
| Secretary | Takahiro Shinada(Tohoku Univ.) |
| Assistant | Hiroya Ikeda(Shizuoka Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] Fully Coupled 3-D Device Simulation of Negative Capacitance FinFETs for Sub 10 nm Integration |
| Sub Title (in English) | |
| Keyword(1) | ferroelectric |
| Keyword(2) | negative capacitance |
| Keyword(3) | technology computer-aided design |
| Keyword(4) | low power |
| Keyword(5) | subthreshold |
| Keyword(6) | steep |
| 1st Author's Name | Hiroyuki Ota |
| 1st Author's Affiliation | The National Institute of Advanced Industrial Science and Technology(AIST) |
| 2nd Author's Name | Tsutomu Ikegami |
| 2nd Author's Affiliation | The National Institute of Advanced Industrial Science and Technology(AIST) |
| 3rd Author's Name | Junichi Hattori |
| 3rd Author's Affiliation | The National Institute of Advanced Industrial Science and Technology(AIST) |
| 4th Author's Name | Koichi Fukuda |
| 4th Author's Affiliation | The National Institute of Advanced Industrial Science and Technology(AIST) |
| 5th Author's Name | Shinji Migita |
| 5th Author's Affiliation | The National Institute of Advanced Industrial Science and Technology(AIST) |
| 6th Author's Name | Akira Toriumi |
| 6th Author's Affiliation | The University of Tokyo(The Univ. of Tokyo) |
| Date | 2017-01-30 |
| Paper # | SDM2016-133 |
| Volume (vol) | vol.116 |
| Number (no) | SDM-448 |
| Page | pp.pp.13-16(SDM), |
| #Pages | 4 |
| Date of Issue | 2017-01-23 (SDM) |