| Presentation | 2017-02-21 IR-Drop Analysis on Different Power Supply Network Designs Kohei Miyase, Kiichi Hamasaki, Matthias Sauer, Ilia Polian, Bernd Becker, Xiaoqing Wen, Seiji kajihara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The shrinking feature size and low power design of LSI make LSI testing very difficult. Further development of LSI technology will lead to thinner wiring width, even for power supply networks and power supply voltage. Currently, vias used between the different layers of a power supply network are redundantly designed; therefore, missing only one via does not cause any problems. However, further shrinkage of feature size and low power design will lead to serious error caused by defects on the power supply network. Even though defects on power supply networks themselves do not cause an error, these defects may increase the possibility of test malfunction, a problem which has recently been actualized. In this paper, we analyze IR-drop on different power supply network designs for IWLS2005 benchmark circuits in order to understand the effect that IR-drop propagates on a chip when a via is missing. Analyzed results will be used in fault diagnosis for power related defects and power controlling test pattern generation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | low power design / power controlling testing / power supply network design / test malfunction / fault diagnosis / test pattern generation |
| Paper # | DC2016-75 |
| Date of Issue | 2017-02-14 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2017/2/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc |
| Chair | Michiko Inoue(NAIST) |
| Vice Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Satoshi Fukumoto(Kyoto Sangyo Univ.) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | IR-Drop Analysis on Different Power Supply Network Designs |
| Sub Title (in English) | |
| Keyword(1) | low power design |
| Keyword(2) | power controlling testing |
| Keyword(3) | power supply network design |
| Keyword(4) | test malfunction |
| Keyword(5) | fault diagnosis |
| Keyword(6) | test pattern generation |
| 1st Author's Name | Kohei Miyase |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Kiichi Hamasaki |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 3rd Author's Name | Matthias Sauer |
| 3rd Author's Affiliation | University of Freiburg(University of Freiburg) |
| 4th Author's Name | Ilia Polian |
| 4th Author's Affiliation | University of Passau(University of Passau) |
| 5th Author's Name | Bernd Becker |
| 5th Author's Affiliation | University of Freiburg(University of Freiburg) |
| 6th Author's Name | Xiaoqing Wen |
| 6th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 7th Author's Name | Seiji kajihara |
| 7th Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2017-02-21 |
| Paper # | DC2016-75 |
| Volume (vol) | vol.116 |
| Number (no) | DC-466 |
| Page | pp.pp.7-10(DC), |
| #Pages | 4 |
| Date of Issue | 2017-02-14 (DC) |