Presentation 2017-02-21
An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination
Daichi Yuruki, Satoshi Ohtake, Yoshiyuki Nakamura,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Today, advancements of semiconductor technology have progress to high integration of LSI circuits. A technique which keeps quality of LSIs and reduces test cost is necessary. In this work, we tackle this problem with machine learning techniques: learning test results of LSIs by machine learning from the test data of LSIs produced in the past, and prediction if a newly produced LSI is good or defective using intermediate test results of the LSI, i.e, the cost of remaining tests for the LSI can be reduced. In this paper, we propose several techniques for distinction precision of good products and defective products for the test cost reduction and evaluate them by performing experiments.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Data mining / clustering / discriminant analysis / LSI testing
Paper # DC2016-77
Date of Issue 2017-02-14 (DC)

Conference Information
Committee DC
Conference Date 2017/2/21(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Kikai-Shinko-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English) VLSI Design and Test, etc
Chair Michiko Inoue(NAIST)
Vice Chair Satoshi Fukumoto(Tokyo Metropolitan Univ.)
Secretary Satoshi Fukumoto(Kyoto Sangyo Univ.)
Assistant

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination
Sub Title (in English)
Keyword(1) Data mining
Keyword(2) clustering
Keyword(3) discriminant analysis
Keyword(4) LSI testing
1st Author's Name Daichi Yuruki
1st Author's Affiliation Oita University(Oita Univ)
2nd Author's Name Satoshi Ohtake
2nd Author's Affiliation Oita University(Oita Univ)
3rd Author's Name Yoshiyuki Nakamura
3rd Author's Affiliation Renesas System Design Co., Ltd.(Renesas System Design)
Date 2017-02-21
Paper # DC2016-77
Volume (vol) vol.116
Number (no) DC-466
Page pp.pp.17-22(DC),
#Pages 6
Date of Issue 2017-02-14 (DC)