| Presentation | 2017-02-21 An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States Morito Niseki, Toshinori Hosokawa, Msayoshi Yoshimura, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Scan design has problems such as large hardware overhead and long test application time. Non-scan based test generation is required to resolve the above mentioned problems. However, it is hard to achieve high fault efficiency using non-scan based test generation and an untestable fault identification is especially time-consuming. Therefore, untestable fault identification methods before test generation have been proposed to reduce test generation time. In this paper, an unreachable state identification method, which identifies whether states on a few flip-flops are justified using SAT, is proposed and an untestable fault identification method is proposed using the unreachable states and time expansion models. Untestable faults are identified by applying the combination of conventional methods and our proposed method to ISCAS’89 benchmark circuits, and the number of untestable faults is evaluated. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | sequential circuits / untestable faults / unreachable states / time expansion models |
| Paper # | DC2016-79 |
| Date of Issue | 2017-02-14 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2017/2/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc |
| Chair | Michiko Inoue(NAIST) |
| Vice Chair | Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Satoshi Fukumoto(Kyoto Sangyo Univ.) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States |
| Sub Title (in English) | |
| Keyword(1) | sequential circuits |
| Keyword(2) | untestable faults |
| Keyword(3) | unreachable states |
| Keyword(4) | time expansion models |
| 1st Author's Name | Morito Niseki |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Msayoshi Yoshimura |
| 3rd Author's Affiliation | Kyoto Sangyo University(Kyoto Sangyo Univ.) |
| 4th Author's Name | Masayuki Arai |
| 4th Author's Affiliation | Nihon University(Nihon Univ.) |
| 5th Author's Name | Hiroyuki Yotsuyanagi |
| 5th Author's Affiliation | Tokushima University(Tokushima Univ.) |
| 6th Author's Name | Masaki Hashizume |
| 6th Author's Affiliation | Tokushima University(Tokushima Univ.) |
| Date | 2017-02-21 |
| Paper # | DC2016-79 |
| Volume (vol) | vol.116 |
| Number (no) | DC-466 |
| Page | pp.pp.29-34(DC), |
| #Pages | 6 |
| Date of Issue | 2017-02-14 (DC) |