Presentation 2017-01-31
A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry
Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which enables 2-read/write (2RW) operation within a clock cycle. We designed and implemented a 512-kb pseudo DP SRAM macro based on 28-nm low-power bulk CMOS technology. Our design achieved the bit density of 5.92 Mb/mm2, which is the highest ever reported.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Pseudo / DP / 2RW / SRAM / 28nm / Double pumping
Paper # EMD2016-86,MR2016-58,SCE2016-64,EID2016-65,ED2016-129,CPM2016-130,SDM2016-129,ICD2016-117,OME2016-98
Date of Issue 2017-01-23 (EMD, MR, SCE, EID, ED, CPM, SDM, ICD, OME)

Conference Information
Committee ICD / CPM / ED / EID / EMD / MR / OME / SCE / SDM
Conference Date 2017/1/30(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Miyajima-Morino-Yado(Hiroshima)
Topics (in Japanese) (See Japanese page)
Topics (in English) Circuit, Device and Engineering Science
Chair Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) / Koichi Maezawa(Univ. of Toyama) / Tomokazu Shiga(Univ. of Electro-Comm.) / Yoshiteru Abe(NTT) / Yoshihiro Okamoto(Ehime Univ.) / Naoki Matsuda(AIST) / Nobuyuki Yoshikawa(Yokohama National Univ.) / Tatsuya Kunikiyo(Renesas)
Vice Chair Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) / Kunio Tsuda(Toshiba) / Mutsumi Kimura(Ryukoku Univ.) / Yuko Kominami(Shizuoka Univ.) / / / Tatsuo Mori(Aichi Inst. of Tech.) / / Takahiro Shinada(Tohoku Univ.)
Secretary Hideto Hidaka(Hiroshima Univ.) / Fumihiko Hirose(Univ. of Tokyo) / Kunio Tsuda(NTT) / Mutsumi Kimura(Nihon Univ.) / Yuko Kominami(JAIST) / (New JRC) / (NTT) / Tatsuo Mori(Tokyo Inst. of Tech.) / (Sumitomo Denso) / Takahiro Shinada(Fujielectric)
Assistant Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Masataka Higashiwaki(NICT) / Toshiyuki Oishi(Saga Univ.) / Rumiko Yamaguchi(Akita Univ.) / Hiroyuki Nitta(Japan Display) / Mitsuru Nakata(NHK) / Takashi Kojiri(ZEON) / Ryosuke Nonaka(Toshiba) / Yoshiki Kayano(Univ. of Electro-Comm.) / Yuichi Hayashi(Tohoku Gakuin Univ.) / Kiwamu Kudo(Toshiba) / Shuhei Yoshida(Kinki Univ.) / Hirotake Kajii(Osaka Univ.) / Dai Taguchi(Tokyo Inst. of Tech.) / Hiroyuki Akaike(Nagoya Univ.) / Yuki Yamanashi(Yokohama National Univ.) / Hiroya Ikeda(Shizuoka Univ.)

Paper Information
Registration To Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials / Technical Committee on Electron Devices / Technical Committee on Electronic Information Displays / Technical Committee on Electromechanical Devices / Technical Committee on Magnetic Recording / Technical Committee on Organic Molecular Electronics / Technical Committee on Superconductive Electronics / Technical Committee on Silicon Device and Materials
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry
Sub Title (in English)
Keyword(1) Pseudo
Keyword(2) DP
Keyword(3) 2RW
Keyword(4) SRAM
Keyword(5) 28nm
Keyword(6) Double pumping
1st Author's Name Yuichiro Ishii
1st Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
2nd Author's Name Makoto Yabuuchi
2nd Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
3rd Author's Name Yohei Sawada
3rd Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
4th Author's Name Masao Morimoto
4th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
5th Author's Name Yasumasa Tsukamoto
5th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
6th Author's Name Yuta Yoshida
6th Author's Affiliation Renesas System Design Co., Ltd.(Renesas System Design)
7th Author's Name Ken Shibata
7th Author's Affiliation Renesas System Design Co., Ltd.(Renesas System Design)
8th Author's Name Toshiaki Sano
8th Author's Affiliation Renesas System Design Co., Ltd.(Renesas System Design)
9th Author's Name Shinji Tanaka
9th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
10th Author's Name Koji Nii
10th Author's Affiliation Renesas Electronics Corporation(Renesas Electronics)
Date 2017-01-31
Paper # EMD2016-86,MR2016-58,SCE2016-64,EID2016-65,ED2016-129,CPM2016-130,SDM2016-129,ICD2016-117,OME2016-98
Volume (vol) vol.116
Number (no) EMD-439,MR-440,SCE-441,EID-442,ED-443,CPM-444,SDM-445,ICD-446,OME-447
Page pp.pp.87-92(EMD), pp.87-92(MR), pp.87-92(SCE), pp.87-92(EID), pp.87-92(ED), pp.87-92(CPM), pp.87-92(SDM), pp.87-92(ICD), pp.87-92(OME),
#Pages 6
Date of Issue 2017-01-23 (EMD, MR, SCE, EID, ED, CPM, SDM, ICD, OME)