| Presentation | 2017-01-24 Implementation of Path Profiler Using Loop Block for Dynamic Behavior Analysis of Nested Loops Yuki Kikuchi, Kanemitsu Ootsu, Takanobu Baba, Takashi Yokota, Takeshi Ohkawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, heterogeneous multi-core processer is spreading. We should exactly understand both staticand dynamic behavior of target programs for realizing effective parallel processing according to core with various characteristics. In particular, the acquisition of dynamic information is indispensable to realize effective parallel processing. We have developed a path profiler which can acquire profile information to realizing effective parallel processing for a loop. However, when the former profiler analyzes nested loops, there is a problem that the analysis except the most inner loop had difficult. It is possible for path profiler by the analysis for each hierarchy for nested loops by introducing a loop block. In this paper, we show the implementation of our profiler, and the operation of the profiler. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | dynamic behavior analysis / loop block / heterogeneous multi-core |
| Paper # | VLD2016-85,CPSY2016-121,RECONF2016-66 |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | CPSY / RECONF / VLD / IPSJ-SLDM / IPSJ-ARC |
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| Conference Date | 2017/1/23(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Chair | Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Takashi Takenana(NEC) / Masahiro Fukui(Ritsumeikan Univ.) / 五島 正裕(NII) |
| Vice Chair | Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Secretary | Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) / Masato Motomura(Univ. of Tsukuba) / Yuichiro Shibata(Hiroshima City Univ.) / Hiroyuki Ochi(Fujitsu Labs.) / (Hiroshima City Univ.) / (Sharp) |
| Assistant | Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(Hokkaido Univ.) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Parizy Matthieu(Fujitsu Labs.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Special Interest Group on System and LSI Design Methodology / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Path Profiler Using Loop Block for Dynamic Behavior Analysis of Nested Loops |
| Sub Title (in English) | |
| Keyword(1) | dynamic behavior analysis |
| Keyword(2) | loop block |
| Keyword(3) | heterogeneous multi-core |
| Keyword(4) | |
| 1st Author's Name | Yuki Kikuchi |
| 1st Author's Affiliation | Utsunomiya University(Utsunomiya Univ.) |
| 2nd Author's Name | Kanemitsu Ootsu |
| 2nd Author's Affiliation | Utsunomiya University(Utsunomiya Univ.) |
| 3rd Author's Name | Takanobu Baba |
| 3rd Author's Affiliation | Utsunomiya University(Utsunomiya Univ.) |
| 4th Author's Name | Takashi Yokota |
| 4th Author's Affiliation | Utsunomiya University(Utsunomiya Univ.) |
| 5th Author's Name | Takeshi Ohkawa |
| 5th Author's Affiliation | Utsunomiya University(Utsunomiya Univ.) |
| Date | 2017-01-24 |
| Paper # | VLD2016-85,CPSY2016-121,RECONF2016-66 |
| Volume (vol) | vol.116 |
| Number (no) | VLD-415,CPSY-416,RECONF-417 |
| Page | pp.pp.103-108(VLD), pp.103-108(CPSY), pp.103-108(RECONF), |
| #Pages | 6 |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) |