| Presentation | 2017-01-23 Optimal Design of FIR filter using a Real Coded Genetic Algorithm Processor Akihiko Tsukahara, Akinori Kanasugi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Evolutionary algorithms such as Genetic Algorithm (GA) are applied to the optimum design of digital filters. In generally, digital filter design using these methods are often implemented by software. Hardware implementation using dedicated hardware has not been reported much yet. In this paper, we report optimal design of FIR filter using RCGA processor. Since the solution candidates are evaluated by the soft macro general-purpose CPU, various filters can be designed by changing the program. Furthermore, since the RCGA processor and finite impulse response (FIR) filter are implemented in one chip FPGA, it can be expected to be applied to embedded application. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Generic Algorithm / Real coded Generic Algorithm / FIR filter / FPGA |
| Paper # | VLD2016-71,CPSY2016-107,RECONF2016-52 |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | CPSY / RECONF / VLD / IPSJ-SLDM / IPSJ-ARC |
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| Conference Date | 2017/1/23(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Chair | Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Takashi Takenana(NEC) / Masahiro Fukui(Ritsumeikan Univ.) / 五島 正裕(NII) |
| Vice Chair | Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hiroyuki Ochi(Ritsumeikan Univ.) |
| Secretary | Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) / Masato Motomura(Univ. of Tsukuba) / Yuichiro Shibata(Hiroshima City Univ.) / Hiroyuki Ochi(Fujitsu Labs.) / (Hiroshima City Univ.) / (Sharp) |
| Assistant | Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(Hokkaido Univ.) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Parizy Matthieu(Fujitsu Labs.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on VLSI Design Technologies / Special Interest Group on System and LSI Design Methodology / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optimal Design of FIR filter using a Real Coded Genetic Algorithm Processor |
| Sub Title (in English) | |
| Keyword(1) | Generic Algorithm |
| Keyword(2) | Real coded Generic Algorithm |
| Keyword(3) | FIR filter |
| Keyword(4) | FPGA |
| 1st Author's Name | Akihiko Tsukahara |
| 1st Author's Affiliation | Tokyo Denki University(Tokyo Denki Univ.) |
| 2nd Author's Name | Akinori Kanasugi |
| 2nd Author's Affiliation | Tokyo Denki University(Tokyo Denki Univ.) |
| Date | 2017-01-23 |
| Paper # | VLD2016-71,CPSY2016-107,RECONF2016-52 |
| Volume (vol) | vol.116 |
| Number (no) | VLD-415,CPSY-416,RECONF-417 |
| Page | pp.pp.7-12(VLD), pp.7-12(CPSY), pp.7-12(RECONF), |
| #Pages | 6 |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) |