Presentation 2016-12-15
[ポスター講演]電力制約型FPGAアクセラレータにおけるマルチレベル実行制御手法の評価
Keisuke Fujimoto, Shinya Takamaeda, Takashi Nakada, Yasuhiko Nakashima,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English)
Paper # ICD2016-57,CPSY2016-63
Date of Issue 2016-12-08 (ICD, CPSY)

Conference Information
Committee ICD / CPSY
Conference Date 2016/12/15(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Tokyo Institute of Technology
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Minoru Fujishima(Hiroshima Univ.) / Yasuhiko Nakashima(NAIST)
Vice Chair Hideto Hidaka(Renesas) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo)
Secretary Hideto Hidaka(Hiroshima Univ.) / Koji Nakano(Univ. of Tokyo) / Hidetsugu Irie(Fujitsu Labs.)
Assistant Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(Hokkaido Univ.)

Paper Information
Registration To Technical Committee on Integrated Circuits and Devices / Technical Committee on Computer Systems
Language JPN-ONLY
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English)
Sub Title (in English)
Keyword(1)
Keyword(2)
Keyword(3)
1st Author's Name Keisuke Fujimoto
1st Author's Affiliation Nara Institute of Sience and Technology(NAIST)
2nd Author's Name Shinya Takamaeda
2nd Author's Affiliation Hokkaido University(Hokkaido Univ.)
3rd Author's Name Takashi Nakada
3rd Author's Affiliation Nara Institute of Sience and Technology(NAIST)
4th Author's Name Yasuhiko Nakashima
4th Author's Affiliation Nara Institute of Sience and Technology(NAIST)
Date 2016-12-15
Paper # ICD2016-57,CPSY2016-63
Volume (vol) vol.116
Number (no) ICD-364,CPSY-365
Page pp.pp.33-33(ICD), pp.33-33(CPSY),
#Pages 1
Date of Issue 2016-12-08 (ICD, CPSY)