| Presentation | 2016-12-15 [Poster Presentation] Reduction of Data-Retention Error in TLC NAND Flash Memories Yuichi Sato, Yoshiaki Deguchi, Atsuro Kobayashi, Ken Takeuchi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The cost of NAND flash memory is reduced by scaling and multi-level cell technologies. However, the reliability of triple-level cell (TLC : 3-bit/cell) NAND flash is degraded due to the narrower read margins. Moreover, due to the write/erase endurance stress, traps which may capture electrons are generated in the tunnel oxide. Data-retention error is caused by ejecting electrons from the floating-gate via traps. Reliability is degraded by scaling since the threshold voltage is more decreased when one electron ejects. This paper reports data-retention error reduction technique of TLC NAND flash memory. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | NAND flash memory / Reliability |
| Paper # | ICD2016-76,CPSY2016-82 |
| Date of Issue | 2016-12-08 (ICD, CPSY) |
| Conference Information | |
| Committee | ICD / CPSY |
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| Conference Date | 2016/12/15(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tokyo Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Minoru Fujishima(Hiroshima Univ.) / Yasuhiko Nakashima(NAIST) |
| Vice Chair | Hideto Hidaka(Renesas) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) |
| Secretary | Hideto Hidaka(Hiroshima Univ.) / Koji Nakano(Univ. of Tokyo) / Hidetsugu Irie(Fujitsu Labs.) |
| Assistant | Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(Hokkaido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Computer Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Poster Presentation] Reduction of Data-Retention Error in TLC NAND Flash Memories |
| Sub Title (in English) | |
| Keyword(1) | NAND flash memory |
| Keyword(2) | Reliability |
| 1st Author's Name | Yuichi Sato |
| 1st Author's Affiliation | Chuo University(Chuo Univ.) |
| 2nd Author's Name | Yoshiaki Deguchi |
| 2nd Author's Affiliation | Chuo University(Chuo Univ.) |
| 3rd Author's Name | Atsuro Kobayashi |
| 3rd Author's Affiliation | Chuo University(Chuo Univ.) |
| 4th Author's Name | Ken Takeuchi |
| 4th Author's Affiliation | Chuo University(Chuo Univ.) |
| Date | 2016-12-15 |
| Paper # | ICD2016-76,CPSY2016-82 |
| Volume (vol) | vol.116 |
| Number (no) | ICD-364,CPSY-365 |
| Page | pp.pp.75-75(ICD), pp.75-75(CPSY), |
| #Pages | 1 |
| Date of Issue | 2016-12-08 (ICD, CPSY) |