| Presentation | 2016-12-15 [Poster Presentation] Error Pattern Analysis among Scaled Generations of NAND Flash Memories Yukiya Sakaki, Yusuke Yamaga, Ken Takeuchi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The capacity of NAND flash memory can be expanded by memory cell scaling. However, bit-errors are increased by memory cell scaling and reliability of NAND flash memory is decreased. NAND flash memory can store the data by injection electrons into the floating-gate. However, due to increases of inter-cell coupling noise and decreases of injection electrons, changes of VTH become remarkable by memory cell scaling. As a result, read-disturb error, program-disturb error, and data-retention error are occurred. This paper analyzes error pattern of some generations of NAND flash memory with various Write/Erase cycle and data-retention time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | NAND flash memory / solid-state-drive / basic properties |
| Paper # | ICD2016-69,CPSY2016-75 |
| Date of Issue | 2016-12-08 (ICD, CPSY) |
| Conference Information | |
| Committee | ICD / CPSY |
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| Conference Date | 2016/12/15(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Tokyo Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Minoru Fujishima(Hiroshima Univ.) / Yasuhiko Nakashima(NAIST) |
| Vice Chair | Hideto Hidaka(Renesas) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) |
| Secretary | Hideto Hidaka(Hiroshima Univ.) / Koji Nakano(Univ. of Tokyo) / Hidetsugu Irie(Fujitsu Labs.) |
| Assistant | Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(Hokkaido Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Computer Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Poster Presentation] Error Pattern Analysis among Scaled Generations of NAND Flash Memories |
| Sub Title (in English) | |
| Keyword(1) | NAND flash memory |
| Keyword(2) | solid-state-drive |
| Keyword(3) | basic properties |
| 1st Author's Name | Yukiya Sakaki |
| 1st Author's Affiliation | Chuo University(Chuo Univ.) |
| 2nd Author's Name | Yusuke Yamaga |
| 2nd Author's Affiliation | Chuo University(Chuo Univ.) |
| 3rd Author's Name | Ken Takeuchi |
| 3rd Author's Affiliation | Chuo University(Chuo Univ.) |
| Date | 2016-12-15 |
| Paper # | ICD2016-69,CPSY2016-75 |
| Volume (vol) | vol.116 |
| Number (no) | ICD-364,CPSY-365 |
| Page | pp.pp.57-57(ICD), pp.57-57(CPSY), |
| #Pages | 1 |
| Date of Issue | 2016-12-08 (ICD, CPSY) |