| Presentation | 2016-12-15 Design and Implementation of FPGA based packet scheduler to satisfy latency requirements of applications Katsushi Kobayashi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Since the exiting Internet lacks a network latency support, large network latencies cause problems degrading customer experience, such on interactive network applications. We have proposed Latency AWare InterNet (LAWIN) network architecture which satisfies various latency requirements from different applications. In this paper, we present the design and implementation of FPGA based packet scheduler which is a EDF derivative one to satisfy per packet latency requirement and to minimize impacts to existing traffic. We also discuss the implementation issues of packet schedulers for future network bandwidth growth. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Internet / Packet Scheduler |
| Paper # | IA2016-68 |
| Date of Issue | 2016-12-08 (IA) |
| Conference Information | |
| Committee | IA / IN |
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| Conference Date | 2016/12/15(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiroshima city university |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Performance Analysis and Simulation, Robustness, Traffic and Throughput Measurement, Quality of Service (QoS) Control, Congestion Control, Overlay Network/P2P, IPv6, Multicast, Routing, DDoS, etc. |
| Chair | Ken-ichi Yoshida(Univ. of Tsukuba) / Katsunori Yamaoka(Tokyo Inst. of Tech.) |
| Vice Chair | Hiroyuki Osaki(Kwansei Gakuin Univ.) / Masahiro Jibiki(NICT) / Tomoki Yoshihisa(Osaka Univ.) / Takuji Kishida(NTT) |
| Secretary | Hiroyuki Osaki(Tokyo Inst. of Tech.) / Masahiro Jibiki(Ritsumeikan Univ.) / Tomoki Yoshihisa(KDDI R&D Labs.) / Takuji Kishida(NTT) |
| Assistant | Yusuke Sakumoto(Tokyo Metropolitan Univ.) / Yuichiro Hei(KDDI R&D Labs.) / Toshiki Watanabe(NEC) / Kunitake Kaneko(Keio Univ.) / Takashi Natsume(NTT) |
| Paper Information | |
| Registration To | Technical Committee on Internet Architecture / Technical Committee on Information Networks |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implementation of FPGA based packet scheduler to satisfy latency requirements of applications |
| Sub Title (in English) | |
| Keyword(1) | Internet |
| Keyword(2) | Packet Scheduler |
| 1st Author's Name | Katsushi Kobayashi |
| 1st Author's Affiliation | The University of Tokyo(University of Tokyo) |
| Date | 2016-12-15 |
| Paper # | IA2016-68 |
| Volume (vol) | vol.116 |
| Number (no) | IA-362 |
| Page | pp.pp.29-34(IA), |
| #Pages | 6 |
| Date of Issue | 2016-12-08 (IA) |