| Presentation | 2016-11-28 Hardware implementation of PLC Instructions by high level synthesis Ishigaki Yoshiki, Tanaka Tasuku, Fujieda Naoki, Ichikawa Shuichi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The hardware implementation of instruction sequence is a method to conceal and to protect the intellectual property. In this study, PLC instructions are synthesized, implemented, and evaluated with Xilinx FPGA and Vivado HLS. The derived designs can be controlled by the directives of Vivado HLS. The reduction of latency was maximally 2% with pipelining, while the logic scale was reduced to 56% of the original by sharing arithmetic units. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Programmable Logic Controller / High Level Synthesis / Hardware Implementation / FPGA |
| Paper # | RECONF2016-43 |
| Date of Issue | 2016-11-21 (RECONF) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE |
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| Conference Date | 2016/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
| Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Satoru Noge(Numazu National College of Tech.) / Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT) |
| Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK) |
| Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Satoshi Fukumoto(Hiroshima City Univ.) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Masato Motomura(Fujitsu Labs.) / Yuichiro Shibata(NII) / Fumihiko Hirose(Univ. of Tsukuba) / Hideto Hidaka(Hiroshima City Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Nihon Univ.) |
| Assistant | Parizy Matthieu(Fujitsu Labs.) / / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Kei Kawamura(KDDI R&D Labs.) / Keita Takahashi(Nagoya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware implementation of PLC Instructions by high level synthesis |
| Sub Title (in English) | |
| Keyword(1) | Programmable Logic Controller |
| Keyword(2) | High Level Synthesis |
| Keyword(3) | Hardware Implementation |
| Keyword(4) | FPGA |
| Keyword(5) | |
| Keyword(6) | |
| 1st Author's Name | Ishigaki Yoshiki |
| 1st Author's Affiliation | toyohashi university of technology(TUT) |
| 2nd Author's Name | Tanaka Tasuku |
| 2nd Author's Affiliation | toyohashi university of technology(TUT) |
| 3rd Author's Name | Fujieda Naoki |
| 3rd Author's Affiliation | toyohashi university of technology(TUT) |
| 4th Author's Name | Ichikawa Shuichi |
| 4th Author's Affiliation | toyohashi university of technology(TUT) |
| Date | 2016-11-28 |
| Paper # | RECONF2016-43 |
| Volume (vol) | vol.116 |
| Number (no) | RECONF-332 |
| Page | pp.pp.19-24(RECONF), |
| #Pages | 6 |
| Date of Issue | 2016-11-21 (RECONF) |