| Presentation | 2016-11-28 Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA Manri Terada, Hayato Mashiko, Yukihide Kohira, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, the logic circuits are implemented to FPGA in many fields. To achieve faster circuits, a design flow to implement general-synchronous circuits that allow to distribute the clock signal at different timings to the registers in FPGA produced by Xilinx has been proposed.However, since the excess margins are often added to work the general-synchronous circuits correctly in the existing method, the performance improvement by the existing method is not enough.Furthermore, in the existing method, since circuits given as the inputs of the flow are represented in gate-level, it is not practical.In this paper, to improve the existing method, we propose a design flow to implement the general-synchronous circuits to FPGA produced by Xilinx by using the engineering change order without adding the excess margins from the RTL representation.Experiment shows the effectiveness of the proposed method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Xilinx FPGA / engineering change order / general-synchronous framework |
| Paper # | VLD2016-48,DC2016-42 |
| Date of Issue | 2016-11-21 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE |
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| Conference Date | 2016/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
| Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Satoru Noge(Numazu National College of Tech.) / Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT) |
| Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK) |
| Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Satoshi Fukumoto(Hiroshima City Univ.) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Masato Motomura(Fujitsu Labs.) / Yuichiro Shibata(NII) / Fumihiko Hirose(Univ. of Tsukuba) / Hideto Hidaka(Hiroshima City Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Nihon Univ.) |
| Assistant | Parizy Matthieu(Fujitsu Labs.) / / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Kei Kawamura(KDDI R&D Labs.) / Keita Takahashi(Nagoya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA |
| Sub Title (in English) | |
| Keyword(1) | Xilinx FPGA |
| Keyword(2) | engineering change order |
| Keyword(3) | general-synchronous framework |
| 1st Author's Name | Manri Terada |
| 1st Author's Affiliation | The University of Aizu(Univ. of Aizu) |
| 2nd Author's Name | Hayato Mashiko |
| 2nd Author's Affiliation | The University of Aizu(Univ. of Aizu) |
| 3rd Author's Name | Yukihide Kohira |
| 3rd Author's Affiliation | The University of Aizu(Univ. of Aizu) |
| Date | 2016-11-28 |
| Paper # | VLD2016-48,DC2016-42 |
| Volume (vol) | vol.116 |
| Number (no) | VLD-330,DC-331 |
| Page | pp.pp.25-30(VLD), pp.25-30(DC), |
| #Pages | 6 |
| Date of Issue | 2016-11-21 (VLD, DC) |