Presentation | 2016-11-30 Design of TDC Embedded in Scan FFs for Testing Small Delay Faults Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures. Small delay faults may cause circuit malfunction due to aging deterioration. Therefore, test method for small delay faults is required. We have proposed small delay measurement circuit using TDC(Time-to-Digital Converter) to detect small delay faults on circuit paths. In this paper, we propose new scan FF design that can from a TDC with less area overhead and evaluate its feasibility to detect small delay faults by circuit simulation. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | small delay faults / TDC(Time-to-Digital Converter) / design for testability / scan design |
Paper # | VLD2016-62,DC2016-56 |
Date of Issue | 2016-11-21 (VLD, DC) |
Conference Information | |
Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE |
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Conference Date | 2016/11/28(3days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Satoru Noge(Numazu National College of Tech.) / Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT) |
Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK) |
Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Satoshi Fukumoto(Hiroshima City Univ.) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Masato Motomura(Fujitsu Labs.) / Yuichiro Shibata(NII) / Fumihiko Hirose(Univ. of Tsukuba) / Hideto Hidaka(Hiroshima City Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Nihon Univ.) |
Assistant | Parizy Matthieu(Fujitsu Labs.) / / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Kei Kawamura(KDDI R&D Labs.) / Keita Takahashi(Nagoya Univ.) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Design of TDC Embedded in Scan FFs for Testing Small Delay Faults |
Sub Title (in English) | |
Keyword(1) | small delay faults |
Keyword(2) | TDC(Time-to-Digital Converter) |
Keyword(3) | design for testability |
Keyword(4) | scan design |
1st Author's Name | Shingo Kawatsuka |
1st Author's Affiliation | Tokushima University(Tokushima Univ.) |
2nd Author's Name | Hiroyuki Yotsuyanagi |
2nd Author's Affiliation | Tokushima University(Tokushima Univ.) |
3rd Author's Name | Masaki Hashizume |
3rd Author's Affiliation | Tokushima University(Tokushima Univ.) |
Date | 2016-11-30 |
Paper # | VLD2016-62,DC2016-56 |
Volume (vol) | vol.116 |
Number (no) | VLD-330,DC-331 |
Page | pp.pp.105-110(VLD), pp.105-110(DC), |
#Pages | 6 |
Date of Issue | 2016-11-21 (VLD, DC) |