Presentation 2016-11-29
Optimal configuration design of SCM and MLC/TLC NAND flash memory in semiconductor storage system
Chihiro Matsui, Yusuke Yamaga, Yusuke Sugiyama, Ken Takeuchi,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In order to manage wide variety of data at high speed, a tri-hybrid storage system has been proposed with using storage class memory (SCM), multi-cell level (MLC)/triple-level cell (TLC) NAND flash memory. SCM can read and write at high speed, but the cost is high. On the other hand, TLC NAND flash has large capacity with low cost, but the reading and writing speed is longer than that of MLC NAND flash. With considering memory characteristics, optimal memory configuration in the tri-hybrid storage is analyzed.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Storage class memory / NAND flash memory / semiconductor storage
Paper # CPM2016-77,ICD2016-38,IE2016-72
Date of Issue 2016-11-22 (CPM, ICD, IE)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE
Conference Date 2016/11/28(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Ritsumeikan University, Osaka Ibaraki Campus
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2016 -New Field of VLSI Design-
Chair Takashi Takenana(NEC) / Michiko Inoue(NAIST) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Satoru Noge(Numazu National College of Tech.) / Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT)
Vice Chair Hiroyuki Ochi(Ritsumeikan Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK)
Secretary Hiroyuki Ochi(Fujitsu Labs.) / Satoshi Fukumoto(Hiroshima City Univ.) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Masato Motomura(Fujitsu Labs.) / Yuichiro Shibata(NII) / Fumihiko Hirose(Univ. of Tsukuba) / Hideto Hidaka(Hiroshima City Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Nihon Univ.)
Assistant Parizy Matthieu(Fujitsu Labs.) / / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Kei Kawamura(KDDI R&D Labs.) / Keita Takahashi(Nagoya Univ.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Optimal configuration design of SCM and MLC/TLC NAND flash memory in semiconductor storage system
Sub Title (in English)
Keyword(1) Storage class memory
Keyword(2) NAND flash memory
Keyword(3) semiconductor storage
1st Author's Name Chihiro Matsui
1st Author's Affiliation Chuo University(Chuo Univ.)
2nd Author's Name Yusuke Yamaga
2nd Author's Affiliation Chuo University(Chuo Univ.)
3rd Author's Name Yusuke Sugiyama
3rd Author's Affiliation Chuo University(Chuo Univ.)
4th Author's Name Ken Takeuchi
4th Author's Affiliation Chuo University(Chuo Univ.)
Date 2016-11-29
Paper # CPM2016-77,ICD2016-38,IE2016-72
Volume (vol) vol.116
Number (no) CPM-333,ICD-334,IE-335
Page pp.pp.7-10(CPM), pp.7-10(ICD), pp.7-10(IE),
#Pages 4
Date of Issue 2016-11-22 (CPM, ICD, IE)