Presentation 2016-11-29
Accurate Lithography Simulation Model based on Deep Learning
Yuki Watanabe, Tetsuaki Matsunawa, Taiki Kimura, Shigeki Nojima,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Lithography simulation is an indispensable technology for today's semiconductor manufacturing processes. To achieve accurate simulation, a model which predicts wafer patterns based on optical features of design patterns has been proposed. However, it is difficult to define appropriate features. This paper proposes a new model using CNN (Convolutional Neural Network) which is a powerful technique from the field of deep learning. The CNN model automatically determines design pattern features, and predicts wafer patterns accurately. Experimental results show proposed CNN model can reduce the prediction error to 30% compared with the conventional method.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Lithography simulation / Resist Model / Deep learning / CNN
Paper # VLD2016-56,DC2016-50
Date of Issue 2016-11-21 (VLD, DC)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE
Conference Date 2016/11/28(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Ritsumeikan University, Osaka Ibaraki Campus
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2016 -New Field of VLSI Design-
Chair Takashi Takenana(NEC) / Michiko Inoue(NAIST) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Satoru Noge(Numazu National College of Tech.) / Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT)
Vice Chair Hiroyuki Ochi(Ritsumeikan Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK)
Secretary Hiroyuki Ochi(Fujitsu Labs.) / Satoshi Fukumoto(Hiroshima City Univ.) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Masato Motomura(Fujitsu Labs.) / Yuichiro Shibata(NII) / Fumihiko Hirose(Univ. of Tsukuba) / Hideto Hidaka(Hiroshima City Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Nihon Univ.)
Assistant Parizy Matthieu(Fujitsu Labs.) / / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Kei Kawamura(KDDI R&D Labs.) / Keita Takahashi(Nagoya Univ.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Accurate Lithography Simulation Model based on Deep Learning
Sub Title (in English)
Keyword(1) Lithography simulation
Keyword(2) Resist Model
Keyword(3) Deep learning
Keyword(4) CNN
1st Author's Name Yuki Watanabe
1st Author's Affiliation Toshiba Corporation(Toshiba)
2nd Author's Name Tetsuaki Matsunawa
2nd Author's Affiliation Toshiba Corporation(Toshiba)
3rd Author's Name Taiki Kimura
3rd Author's Affiliation Toshiba Corporation(Toshiba)
4th Author's Name Shigeki Nojima
4th Author's Affiliation Toshiba Corporation(Toshiba)
Date 2016-11-29
Paper # VLD2016-56,DC2016-50
Volume (vol) vol.116
Number (no) VLD-330,DC-331
Page pp.pp.73-78(VLD), pp.73-78(DC),
#Pages 6
Date of Issue 2016-11-21 (VLD, DC)