Presentation 2016-11-29
[Keynote Address] CMOS Annealing Machine to Solve Combinatorial Optimization Problems for IoT Era
Masanao Yamaoka,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A new computing machine, CMOS annealing machine, using Ising model that effectively solves combinatorial optimization problems is proposed. The annealing machine maps problems to an Ising model, a model to express the behavior of magnetic spins, and solves the problems by its own convergence property. The convergence is performed by CMOS circuits operations. The prototype chips achieve 100MHz operation and the operation to solve problems using Ising model is confirmed. The power efficiency of the chip is 1800-times higher than that of the conventional Von-Neumann computers.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Ising model / Combinatorial optimization problem / SRAM / non Von-Neumann computer
Paper # VLD2016-59,CPM2016-81,ICD2016-42,IE2016-76,CPSY2016-52,DC2016-53,RECONF2016-49
Date of Issue 2016-11-21 (VLD, DC, RECONF), 2016-11-22 (CPM, ICD, IE, CPSY)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE
Conference Date 2016/11/28(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Ritsumeikan University, Osaka Ibaraki Campus
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2016 -New Field of VLSI Design-
Chair Takashi Takenana(NEC) / Michiko Inoue(NAIST) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Satoru Noge(Numazu National College of Tech.) / Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT)
Vice Chair Hiroyuki Ochi(Ritsumeikan Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK)
Secretary Hiroyuki Ochi(Fujitsu Labs.) / Satoshi Fukumoto(Hiroshima City Univ.) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Masato Motomura(Fujitsu Labs.) / Yuichiro Shibata(NII) / Fumihiko Hirose(Univ. of Tsukuba) / Hideto Hidaka(Hiroshima City Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Nihon Univ.)
Assistant Parizy Matthieu(Fujitsu Labs.) / / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Kei Kawamura(KDDI R&D Labs.) / Keita Takahashi(Nagoya Univ.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) [Keynote Address] CMOS Annealing Machine to Solve Combinatorial Optimization Problems for IoT Era
Sub Title (in English)
Keyword(1) Ising model
Keyword(2) Combinatorial optimization problem
Keyword(3) SRAM
Keyword(4) non Von-Neumann computer
1st Author's Name Masanao Yamaoka
1st Author's Affiliation Hitachi, Ltd.(Hitachi)
Date 2016-11-29
Paper # VLD2016-59,CPM2016-81,ICD2016-42,IE2016-76,CPSY2016-52,DC2016-53,RECONF2016-49
Volume (vol) vol.116
Number (no) VLD-330,CPM-333,ICD-334,IE-335,CPSY-336,DC-331,RECONF-332
Page pp.pp.91-96(VLD), pp.25-30(CPM), pp.25-30(ICD), pp.25-30(IE), pp.27-32(CPSY), pp.91-96(DC), pp.49-54(RECONF),
#Pages 6
Date of Issue 2016-11-21 (VLD, DC, RECONF), 2016-11-22 (CPM, ICD, IE, CPSY)