Presentation 2016-11-28
Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB)
Shunsuke Kogure, Kimiyoshi Usami,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Level shifter is a circuit that changes the voltage amplitude of the signal. It is essential to exchange signals with different power supply voltage area. Level-shifter has the overhead, such as increase in the number of input signals and the circuit area. If the signal connection is possible between the different power supply voltage without inserting a level-shifter, it is possible to eliminate the overhead. In this paper, we propose a method which does not use level-shifters (level-shifter-less method) by applying body bias and Silicon-on-Thin-BOX. Feasibility studies and evaluation for level-shifter-less design is demonstrated by simulation and real chip.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Level-shifter-less / Body Bias / Silicon-on-Thin-Box(SOTB)
Paper # VLD2016-47,DC2016-41
Date of Issue 2016-11-21 (VLD, DC)

Conference Information
Committee VLD / DC / CPSY / RECONF / CPM / ICD / IE
Conference Date 2016/11/28(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Ritsumeikan University, Osaka Ibaraki Campus
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2016 -New Field of VLSI Design-
Chair Takashi Takenana(NEC) / Michiko Inoue(NAIST) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Satoru Noge(Numazu National College of Tech.) / Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT)
Vice Chair Hiroyuki Ochi(Ritsumeikan Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK)
Secretary Hiroyuki Ochi(Fujitsu Labs.) / Satoshi Fukumoto(Hiroshima City Univ.) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Masato Motomura(Fujitsu Labs.) / Yuichiro Shibata(NII) / Fumihiko Hirose(Univ. of Tsukuba) / Hideto Hidaka(Hiroshima City Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Nihon Univ.)
Assistant Parizy Matthieu(Fujitsu Labs.) / / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Kei Kawamura(KDDI R&D Labs.) / Keita Takahashi(Nagoya Univ.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB)
Sub Title (in English)
Keyword(1) Level-shifter-less
Keyword(2) Body Bias
Keyword(3) Silicon-on-Thin-Box(SOTB)
1st Author's Name Shunsuke Kogure
1st Author's Affiliation Shibaura Institute of Technology(Shibaura Institute of Tech)
2nd Author's Name Kimiyoshi Usami
2nd Author's Affiliation Shibaura Institute of Technology(Shibaura Institute of Tech)
Date 2016-11-28
Paper # VLD2016-47,DC2016-41
Volume (vol) vol.116
Number (no) VLD-330,DC-331
Page pp.pp.19-24(VLD), pp.19-24(DC),
#Pages 6
Date of Issue 2016-11-21 (VLD, DC)